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    Method for reducing the settling time in PLL circuits
    5.
    发明公开
    Method for reducing the settling time in PLL circuits 有权
    Verfahren zur Reduzierung der Einschwingzeit von PLL Schaltungen

    公开(公告)号：EP0993122A1

    公开(公告)日：2000-04-12

    申请号：EP98830586.8

    申请日：1998-10-06

    Applicant: STMicroelectronics S.r.l.

    Inventor： Filoramo, Pietro ,  Cosentino, Gaetano

    IPC: H03L7/10 ,  H03L7/189 ,  H03J5/02

    CPC classification number: H03L7/189

    Abstract: A method for reducing the settling time in PLL circuits, particularly for use in an RF transceiver, which comprise a phase comparator (2), a filter (4), a digital-analog converter (8) and an adder (5) which are suitable to produce in output a voltage (V c ) for controlling a voltage-controlled oscillator (6) provided by means of a varactor, characterized in that it comprises the steps of:

    -- determining the dependency of the control voltage (V c ) of the voltage-controlled oscillator (6) on the frequency of a selected channel of a transmitter;
    -- generating a law describing the variation of the output current (I DAC ) of said digital-analog converter (8) such that the voltage (V DAC ) obtained from the output current of the digital-analog converter, added to an output voltage (V f ) of said filter (4), is such as to keep said filter voltage (V f ) constant, in order to reduce the settling time of the PLL circuit as a selected channel varies.

    Abstract translation: 一种用于减少PLL电路中的建立时间的方法，特别是用于RF收发器中的方法，其包括相位比较器（2），滤波器（4），数模转换器（8）和加法器（5） 适于在输出中产生用于控制由变容二极管提供的压控振荡器（6）的电压（Vc），其特征在于包括以下步骤：确定电压 - 电压的控制电压（Vc） 控制振荡器（6）在发射机的选定信道的频率上; 产生描述所述数模转换器（8）的输出电流（IDAC）的变化的定律，使得从数模转换器的输出电流获得的电压（VDAC）加到输出电压（Vf）上 所述滤波器（4）为了保持所述滤波器电压（Vf）恒定，以便随着所选择的信道变化而减小PLL电路的建立时间。

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