公开(公告)号：EP1363330A3

公开(公告)日：2004-10-20

申请号：EP03425299.9

申请日：2003-05-12

Applicant: STMicroelectronics S.r.l.

Inventor： Aiello, Natale ,  Patti, Davide

IPC: H01L27/02 ,  H01L29/94

CPC classification number: H01L27/0676 ,  H01L29/94

Abstract: A capacitor for sensing the substrate voltage is efficiently and economically realized simply by isolating a portion or segment of the metal layer that normally covers the heavily doped perimetral region of electric field equalization and, in correspondence of such a metal segment isolated by the remaining portion, by not removing preventively the isolation dielectric layer of silicon oxide from the surface of the semiconductor substrate, as it is normally done on the remaining portion of the perimetral edge region before depositing the metal. The unremoved layer of isolated silicon oxide (12) becomes the dielectric layer of the so constituted capacitor, a plate of which is the heavily doped perimetral region (4) that is electrically connected to the substrate (drain or collector region) while the other plate is constituted by the segment of metal (4'), isolated from the remaining metal layer defined directly over the heavily doped perimetral region (4).

公开(公告)号：EP1005091B1

公开(公告)日：2002-07-10

申请号：EP98830690.8

申请日：1998-11-17

Applicant: STMicroelectronics S.r.l.

Inventor： Patti, Davide ,  Pinto, Angelo

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66666 ,  H01L21/76221 ,  H01L21/763 ,  H01L21/8249 ,  H01L29/7827

公开(公告)号：EP1005092A1

公开(公告)日：2000-05-31

申请号：EP98830710.4

申请日：1998-11-26

Applicant: STMicroelectronics S.r.l.

Inventor： Ronsisvalle, Cesare ,  Fallica, Piero Giorgio ,  Patti, Davide

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/868 ,  H01L21/18 ,  H01L21/762 ,  H01L21/32

CPC classification number: H01L29/7802 ,  H01L21/762 ,  H01L29/0653

Abstract: PN junction structure comprising a first junction region (1) of a first conductivity type, and a second junction region (2) of a second conductivity type, characterized in that between said first and second junction regions (1,2) a grid of buried insulating materials regions (6;6A;6B;6C) is provided. The structure is applied to a MOS-based device. A method for its manufacturing is proposed.

Abstract translation: PN结结构，其包括第一导电类型的第一结区（1）和第二导电类型的第二结区（2），其特征在于，在所述第一和第二连接区域（1,2）之间埋设栅格 提供绝缘材料区域（6; 6A; 6B; 6C）。 该结构应用于基于MOS的器件。 提出了一种制造方法。

公开(公告)号：EP0878848A1

公开(公告)日：1998-11-18

申请号：EP97830228.9

申请日：1997-05-16

Applicant: STMicroelectronics S.r.l.

Inventor： Patti, Davide

IPC: H01L29/73 ,  H01L21/331

CPC classification number: H01L29/66303 ,  H01L29/0804 ,  H01L29/7304

Abstract: The transistor (20) comprises: an epitaxial layer (22, 25) with a first conductivity type; a base buried region (23) with a second conductivity type; a sinker base region (26) with the second conductivity type, which extends from the main surface (25a) to the buried base region, and delimits, together with the base buried region, emitter fingers (27) in the epitaxial layer; an emitter buried region (24) with the first conductivity type and a doping level which is higher than that of the epitaxial layer, said emitter buried region (24) being embedded in the epitaxial layer in a position adjacent to the base buried region; and a sinker emitter region (28) having the first conductivity type and a doping level which is higher than that of the epitaxial layer and extending from the main surface to the emitter buried region inside the emitter fingers. The buried and sinker emitter regions delimit in each finger pairs of sections (24d, 28a) which are mutually spaced and delimit between one another a central region (25b) of epitaxial layer. The sinker emitter region sections (28a) of a finger extend in the vicinity of mutually facing edges of the emitter buried region sections (24d).

Abstract translation: 晶体管（20）包括：具有第一导电类型的外延层（22，25）; 掩埋基极区域（23）具有第二导电类型; 沉降片基极区域（26）与所述第二导电类型，其中从主表面（25A）到掩埋基区延伸，并且限定，与基掩埋区一起，发射器在所述外延层的手指（27）; 与所述第一导电类型和掺杂水平的所有其比所述外延层的更高到发射极埋入区（24），所述发射极埋入区（24）被嵌在邻近基埋入区的位置上的外延层; 并且具有所述第一导电类型的下沉发射极区域（28）和一个掺杂水平的所有其比所述外延层的和更高的从主表面延伸到发射极埋入区的指状发射极的内部。 掩埋和下沉发射极区限定在其中相互隔开的部分（24D，28A）的每个手指对和彼此外延层（25b）的中央区域之间限定。 发射器的手指的区域的部分（28a）的沉降片在发射极埋入区的部分（24D）的相互面对的边缘的附近延伸。