公开(公告)号：EP1043769A1

公开(公告)日：2000-10-11

申请号：EP99830199.8

申请日：1999-04-07

Applicant: STMicroelectronics S.r.l.

Inventor： Fallica, Piero Giorgio ,  Patti, Davide Giuseppe ,  Rapisarda, Cirino

IPC: H01L21/762 ,  H01L21/763

CPC classification number: H01L21/76232 ,  H01L21/763

Abstract: The process comprises the steps of: carrying out a directional etching, in a semiconductor material body (2, 3), to form trenches (10, 10a) having a first width; carrying out an isotropic etching of the semiconductor material body (2, 3) under the trenches (10, lOa) to form cavities (13; 13a; 13b) having a width larger than the trenches; covering the walls of the cavities with dielectric material (17a; 17b; 17c); depositing non-conducting material different from thermal oxide to fill said cavities at least partially, so as to form a single-crystal island (16) separated from the rest of the semiconductor material body (2, 3). The isotropic etching permits the formation of at least two adjacent cavities (13a, 13b) separated by a support region (25) of semiconductor material which is oxidized (26) together with the walls of the cavities to provide a support to the island (16) prior to filling with non-conducting material.

Abstract translation: 该方法包括以下步骤：执行一方向性蚀刻，在半导体材料体（2，3），以形成沟槽（10，10A），其具有第一宽度; 进行半导体材料主体的各向同性蚀刻的（2，3）在沟槽下（10，图10a），以形成空腔（13; 13A; 13B），其具有的宽度大于所述沟槽较大; 覆盖有电介质材料的空腔的壁（17A; 17B; 17C）; 沉积非导电材料从热氧化物不同填充所述空腔至少部分地，以形成从所述半导体材料体的其余部分分离的单晶冰岛（16）（2，3）。 各向同性蚀刻允许至少两个相邻空腔的形成（13A，13B）由半导体材料制成的支承区域（25）中分离的所有被氧化（26）与腔室的壁以向冰岛的支撑一起（16 ）之前的非导电材料填充。

公开(公告)号：EP1005092A1

公开(公告)日：2000-05-31

申请号：EP98830710.4

申请日：1998-11-26

Applicant: STMicroelectronics S.r.l.

Inventor： Ronsisvalle, Cesare ,  Fallica, Piero Giorgio ,  Patti, Davide

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/868 ,  H01L21/18 ,  H01L21/762 ,  H01L21/32

CPC classification number: H01L29/7802 ,  H01L21/762 ,  H01L29/0653

Abstract: PN junction structure comprising a first junction region (1) of a first conductivity type, and a second junction region (2) of a second conductivity type, characterized in that between said first and second junction regions (1,2) a grid of buried insulating materials regions (6;6A;6B;6C) is provided. The structure is applied to a MOS-based device. A method for its manufacturing is proposed.

Abstract translation: PN结结构，其包括第一导电类型的第一结区（1）和第二导电类型的第二结区（2），其特征在于，在所述第一和第二连接区域（1,2）之间埋设栅格 提供绝缘材料区域（6; 6A; 6B; 6C）。 该结构应用于基于MOS的器件。 提出了一种制造方法。