公开(公告)号：EP1699055B1

公开(公告)日：2010-01-06

申请号：EP05101660.8

申请日：2005-03-03

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico ,  Bolandrina, Efrem ,  Vimercati, Daniele

IPC: G11C11/56 ,  G11C16/28

CPC classification number: G11C11/5642 ,  G11C16/32 ,  G11C2211/5634

公开(公告)号：EP1826766B1

公开(公告)日：2009-09-30

申请号：EP06425124.2

申请日：2006-02-28

Applicant: STMicroelectronics S.r.l.

Inventor： Vimercati, Daniele ,  Bolandrina, Efrem ,  Garofalo, Pierguido

IPC: G11C5/14 ,  G05F3/20

CPC classification number: G05F3/30 ,  G11C5/147

公开(公告)号：EP1826766A1

公开(公告)日：2007-08-29

申请号：EP06425124.2

申请日：2006-02-28

Applicant: STMicroelectronics S.r.l.

Inventor： Vimercati, Daniele ,  Bolandrina, Efrem ,  Garofalo, Pierguido

IPC: G11C5/14 ,  G05F3/20

CPC classification number: G05F3/30 ,  G11C5/147

Abstract: A method is described for generating a controlled current by means of a Band Gap circuitry (10) comprising the steps of:
- supplying on a Band Gap node (BGAP), a Band Gap voltage signal that is stable in temperature and power supply;
- driving a controlled current generator (2) by means of this Band Gap voltage signal; and
mirroring the controlled current signal generated on an output terminal of the Band Gap circuitry;
Advantageously according to the invention, the method further comprises, after the driving step, a step of locally suppressing a disturb of the controlled current signal generated by the controlled current generator (2) by means of a disturb suppression circuit (11) connected to said Band Gap node acting on said Band Gap voltage signal.
A disturb suppression circuit and a Band Gap circuitry for the generation of a controlled current signal are also described.

Abstract translation: 描述了一种方法，用于产生由带隙电路（10）的方式受控电流，包括以下步骤： - 供给的带隙节点（BGAP）上，做了一个带隙电压信号是在温度和电源稳定; - 由该带隙电压信号来驱动受控电流发生器（2）; 以及在带隙电路的输出端子镜像受控电流信号生成的上; 有利的是雅丁到本发明，该方法还包括，在驱动步骤中，通过一个干扰抑制电路的方式局部地抑制由受控电流发生器（2）中产生的控制电流信号的干扰的工序（11）后连接到所述 带隙节点作用在所述带隙电压信号。 因此描述的干扰抑制电路和一个带隙电路，用于控制电流信号的生成。

公开(公告)号：EP1750281A1

公开(公告)日：2007-02-07

申请号：EP05425564.1

申请日：2005-07-29

Applicant: STMicroelectronics S.r.l.

Inventor： Bolandrina, Efrem ,  Vimercati, Daniele ,  Villa, Corrado

IPC: G11C16/28 ,  G11C11/56

CPC classification number: G11C11/5642 ,  G11C16/28 ,  G11C2211/5621 ,  G11C2211/5634

Abstract: A memory device includes a group (11, 17) of memory cells (12) organized in rows and columns and a first addressing circuit (14, 15) for addressing said memory cells (12) of said group (11, 17) on the basis of a cell address (ADD, AWL, ABL). The device further includes a plurality of sets of reference cells (19, 24), associated to the group (11, 17), each of said set having a plurality of reference cells (25a-25c, 26a-26c, 27, 28), and a second addressing circuit (20, 21) for addressing one of the reference cells (25a-25c, 26a-26c, 27, 28) during operations of read and verify of addressed memory cells (12).

Abstract translation: 存储器件包括以行和列组织的存储器单元（12）的组（11,17）和用于对所述组（11,17）的所述存储器单元（12）进行寻址的第一寻址电路（14,15） 单元地址（ADD，AWL，ABL）的基础。 所述装置还包括与所述组（11,17）相关联的多组参考单元（19,24），所述组中的每一组具有多个参考单元（25a-25c，26a-26c，27,28） 以及用于在寻址和验证寻址的存储器单元（12）的操作期间寻址参考单元（25a-25c，26a-26c，27,28）之一的第二寻址电路（20,21）。

公开(公告)号：EP1484764B1

公开(公告)日：2006-08-16

申请号：EP03425353.4

申请日：2003-06-04

Applicant: STMicroelectronics S.r.l.

Inventor： Schippers, Stefan ,  Vimercati, Daniele ,  Bolandrina, Efrem

IPC: G11C7/14 ,  G11C16/28

CPC classification number: G11C16/28 ,  G11C7/14

公开(公告)号：EP1467377A1

公开(公告)日：2004-10-13

申请号：EP03425224.7

申请日：2003-04-10

Applicant: STMicroelectronics S.r.l.

Inventor： Vimercati, Daniele

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G11C16/32 ,  G11C2211/5634

Abstract: A reading method for a nonvolatile memory device (1), wherein the gate terminals of the array memory cell (3) and of the reference memory cell (7) are supplied with a same reading voltage (V READ ) having a ramp-like pattern, so as to modify their current-conduction states in successive times, and the contents of the array memory cell (3) are determined on the basis of the modification order of the current-conduction states of the array memory cell (3) and of the reference memory cell (7).

Abstract translation: 一种用于非易失性存储器件（1）的读取方法，其中阵列存储单元（3）和参考存储单元（7）的栅极端子被提供有具有斜坡图案的相同读取电压（VREAD） 以便连续地修改其导通状态，并且基于阵列存储单元（3）的导通状态的修改顺序和阵列存储单元（3）的电流导通状态的修改顺序来确定阵列存储单元（3）的内容 参考存储单元（7）。