公开(公告)号：EP1505605A1

公开(公告)日：2005-02-09

申请号：EP03017939.4

申请日：2003-08-06

Applicant: STMicroelectronics S.r.l.

Inventor： Vimercati, Daniele ,  Fiorina, Sara ,  Bolandrina, Efrem ,  Schippers, Stefan ,  Onorato, Marco

IPC: G11C7/06 ,  G11C7/12 ,  G11C16/28 ,  G11C16/24

CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C16/24 ,  G11C16/28

Abstract: A sensing circuit (101;301) for a semiconductor memory comprising a circuit branch (109;309) intended to be electrically coupled to a memory bit line (BL) having connected thereto a memory cell (MC) to be sensed. A bit line precharge circuit (117;317) is provided, for precharging the memory bit line to a predetermined potential in a precharge phase of a memory cell sensing operation. An evaluation circuit (117;317) is associated with the memory bit line for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation; the electric quantity that develops on the memory bit line is indicative of an information content of the memory cell. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, so that the predetermined bit line potential is reached irrespective of a memory bit line initial potential at the beginning of the precharge phase. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, depending on a difference between a memory bit line potential and the predetermined bit line potential. At least the precharge circuit includes a precharge negative feedback control loop (119,N4;327,R), for controlling the memory bit line potential during the precharge phase. A same circuit element (119;327,R) is provided that controls the memory bit line potential during the precharge phase and evaluates the electric quantity during the evaluation phase of the memory cell sensing operation.

Abstract translation: 一种用于半导体存储器，其包括一电路支路（109; 309）;感测电路（301 101），用于被电耦合到存储器的位线（BL），其具有与其连接的存储单元（MC）将被感测。 位线预充电电路（117; 317）被提供，用于预充电的存储器的位线到预定电势中的存储器单元的感测操作的预充电阶段。 评估电路（117; 317）与所述存储器的位线相关联，用于在存储单元感测操作的评估阶段期间电量在存储器位线的发展评价; 电量没有开发出在存储器位线指示所述存储器单元中的信息内容。 位线预充电电路是angepasst到两个充电和放电的存储位线，所以DASS模具预定到达位线电位无关的存储器位线的初始电位的预充电阶段的开始。 位线预充电电路是angepasst到两个充电和放电的存储位线，这取决于存储器位线电位和预定位线电位之间的差。 至少所述预充电电路包括：预充电的负反馈控制环（119，N4，327，R），用于在预充电阶段控制所述存储器位线电位。 同一电路元件;设置（119 327，R）预充电阶段期间没有控制存储器位线电位，并在该存储单元读出操作的评估阶段评估电量。

公开(公告)号：EP1473738B1

公开(公告)日：2009-11-04

申请号：EP03425264.3

申请日：2003-04-30

Applicant: STMicroelectronics S.r.l.

Inventor： Vimercati, Daniele ,  Schippers, Stefan ,  Mirichigni, Graziano ,  Villa, Corrado

IPC: G11C16/08 ,  G11C8/08

CPC classification number: G11C8/08 ,  G11C16/08

公开(公告)号：EP1473738A1

公开(公告)日：2004-11-03

申请号：EP03425264.3

申请日：2003-04-30

Applicant: STMicroelectronics S.r.l.

Inventor： Vimercati, Daniele ,  Schippers, Stefan ,  Mirichigni, Graziano ,  Villa, Corrado

IPC: G11C16/08 ,  G11C8/08

CPC classification number: G11C8/08 ,  G11C16/08

Abstract: A circuit (300) is proposed for driving a memory line (110) controlling at least one memory cell (105) of a non-volatile memory device (100), the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter (120s) for converting the first selection signal into a first operative signal and a second level shifter (120g) for converting the second selection signal into a second operative signal, each level shifter including first shifting means (210s, 210g) for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector (140) for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means (305s, 305g) for shifting another of the logic values of the corresponding selection signal to the second bias voltage.

Abstract translation: 一种电路（300）提出了一种用于驱动控制的非易失性存储器装置（100）中的至少一个存储单元（105）的存储器线（110），该电路响应于第一和第二选择信号，每一个 适合于采用第一逻辑值，或第二逻辑值，worin电路包括用于将第一选择信号转换成第一操作信号和用于第二选择信号转换为第二电平移位器（120克）第一电平移位器（120秒） 的第二操作信号，各电平移位器包括用于移动相应的选择信号的逻辑值中的一个到第一偏置电压的第一移位装置（210S，210克），以及用于将所述第一操作信号或第二选择器（140） 偏置电压施加到所述存储器线gemäß到所述第二操作信号; 在发明的电路中的每个电平移位器还包括第二移动装置（305S，305克），用于另一个相应的选择信号的逻辑值的转移到第二偏置电压。

公开(公告)号：EP1835618A1

公开(公告)日：2007-09-19

申请号：EP06425173.9

申请日：2006-03-16

Applicant: STMicroelectronics S.r.l.

Inventor： Vimercati, Daniele ,  Schippers, Stefan ,  Villa, Corrado ,  Zambelli, Yuri

IPC: H03K5/15 ,  G06F1/10

CPC classification number: H03K5/15013

Abstract: Cumulative delay contributions introduced by an input buffer and by the metal line that distributes the buffered external control signal to a plurality of synchronizing and/or enabling circuits for performing a transfer of data to and from an integrated device, can be significantly reduced by having the external signal applied on a pad distributed unbuffered through a metal line of sufficiently large size (conductivity) such to introduce a negligible intrinsic propagation delay, though fulfilling the specified maximum admitted input pad capacitance, and by realizing locally dedicated input buffers to each of a plurality of synchronizing and/or enabling circuits of data transfer of the integrated device for applying thereto a buffered replica of the external signal present on said distributing metal line.

Abstract translation: 通过在INPUTBUFFER和由含金属的引入累积延迟的贡献没有分配缓冲的外部控制信号，以同步和/或使能电路在集成设备执行传输数据的向和从的复数，可以显着地由具有减少的 应用上的焊盘的外部信号通过寻求以引入可忽略的固有传播延迟足够大的尺寸（导电率）的金属线分布缓冲，虽然满足规定的最大承认输入衬垫电容，并且通过实现本地专用输入缓冲器的每一个的多个 的同步和/或使该集成器件的数据传送电路，用于向其施加存在于所述分配含金属的外部信号的缓冲的复制品。

公开(公告)号：EP1484764A1

公开(公告)日：2004-12-08

申请号：EP03425353.4

申请日：2003-06-04

Applicant: STMicroelectronics S.r.l.

Inventor： Schippers, Stefan ,  Vimercati, Daniele ,  Bolandrina, Efrem

IPC: G11C7/14 ,  G11C16/28

CPC classification number: G11C16/28 ,  G11C7/14

Abstract: A method is described for generating a reference current (Iref) for sense amplifiers (11) connected to cells (12) of a memory matrix (1) comprising the steps of:

generating a first reference current analogue signal (REF) through a reference cell (14).

Advantageously according to the invention, the method further comprises the steps of:

performing an Analog-to-Digital conversion of the first analogue signal (REF) into a reference current digital signal (REF_BIT[3:0]);
sending the digital signal (REF_BIT[3:0]) on a connection line (43) to the sense amplifiers (11); and
performing a Digital-to-Analog conversion of the digital signal (REF_BIT[3:0]) into a second reference current analogue signal (REF1) to be applied as reference current (Iref) to the sense amplifiers (11).

The invention also relates to a reference current generator effective to implement this method.

Abstract translation: 描述了一种方法，用于产生连接到存储器矩阵的单元（12），用于读出放大器的参考电流（IREF）（11）（1），包括以下步骤：通过一个参考单元产生第一参考电流的模拟信号（REF） （14）。 有利地gemäß到本发明，该方法还包括以下步骤：执行在模拟到数字的第一模拟信号（REF）成参考电流数字信号（REF_BITÄ3：0U）的转换; 上的连接线（43）连接到读出放大器（11）：（0UREF_BITÄ3）;将所述数字信号 和执行数字信号（REF_BITÄ3：0U）的数字 - 模拟转换为第二参考电流的模拟信号（REF1）作为要应用的基准电流（I REF）到读出放大器（11）。 本发明因此涉及到参考电流发生器有效地实现此方法。

公开(公告)号：EP0766256B1

公开(公告)日：1999-12-01

申请号：EP95830407.3

申请日：1995-09-29

Applicant: STMicroelectronics S.r.l.

Inventor： Tassan Caser, Fabio ,  Schippers, Stefan ,  Cane, Marcello

IPC: G11C16/06 ,  G11C5/14

CPC classification number: G11C16/30 ,  G11C5/147

公开(公告)号：EP1484764B1

公开(公告)日：2006-08-16

申请号：EP03425353.4

申请日：2003-06-04

Applicant: STMicroelectronics S.r.l.

Inventor： Schippers, Stefan ,  Vimercati, Daniele ,  Bolandrina, Efrem

IPC: G11C7/14 ,  G11C16/28

CPC classification number: G11C16/28 ,  G11C7/14

公开(公告)号：EP1220225A1

公开(公告)日：2002-07-03

申请号：EP00830855.3

申请日：2000-12-28

Applicant: STMicroelectronics S.r.l.

Inventor： Riva Reggiori, Riccardo ,  Schippers, Stefan ,  Sali, Mauro

IPC: G11C7/10 ,  G11C16/26

CPC classification number: G11C16/26 ,  G06F12/0893 ,  G11C7/1033

Abstract: The invention relates to a method and a device for reducing the average access time of a non-volatile memory during the reading phase, whereby a reading is effected, in either the page mode or the burst mode, from a matrix array (2) of memory cells to which a logic for recognizing access addresses to the memory is associated. The method is characterized by:

providing a buffer memory (4) associated with the cell matrix array (2), and
storing a predetermined number (n) of memory words into the buffer memory (4) subsequently to a last-effected reading of the cell matrix array (2).

Abstract translation: 本发明涉及一种方法和用于降低在读取阶段，由此读出在任一的页面模式或突发模式实现的非易失性存储器的平均访问时间，从的矩阵阵列（2）的装置 存储器单元哪用于识别存取地址到所述存储器的逻辑相关联。 该方法的特点是：提供一个缓冲存储器（4）与所述单元矩阵阵列（2），和存储内存中的字的预定数目（n）存储在缓冲存储器（4）关联随后的最后一实现读 单元矩阵阵列（2）。

公开(公告)号：EP0766255B1

公开(公告)日：2000-01-26

申请号：EP95830406.5

申请日：1995-09-29

Applicant: STMicroelectronics S.r.l.

Inventor： Sali, Mauro ,  Tassan Caser, Fabio ,  Schippers, Stefan

IPC: G11C16/06 ,  G11C29/00

CPC classification number: G11C16/24 ,  G11C16/10 ,  G11C29/34