公开(公告)号：EP1524810A1

公开(公告)日：2005-04-20

申请号：EP03425663.6

申请日：2003-10-13

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Francesco ,  Notarangelo, Giuseppe ,  Visalli, Giuseppe

IPC: H04L25/49 ,  H04B10/155

CPC classification number: H04B10/5055 ,  H04B10/503 ,  H04B10/516 ,  H04B10/801 ,  H04L25/4915

Abstract: In a method for transmitting on an optical connection (16) a sequence of input data (b(t)) comprising first ("1") and second ("0") logic states, there is envisaged the operation of providing an optical source (15) for generating an optical signal to be transmitted on said optical connection (16), said optical source (15) being able to generate optical pulses at the occurrence of said first ("1") logic states. The method comprises the operation of:
      - encoding (470,570) said sequence of input data (b(t)) in an encoded sequence of data (B(t)) prior to transmission on said optical connection (16), where said encoding operation minimizes the first logic states ("1") in said encoded sequence of data (B(t)).
A preferential application is to optical-fibre communication systems with on-chip integrated buses.

Abstract translation: 在用于在光学连接（16）上发送包括第一（“1”）和第二（“0”）逻辑状态的输入数据序列（b（t））的方法中，设想提供光源 （15），用于产生要在所述光学连接（16）上传输的光信号，所述光源（15）能够在出现所述第一（“1”）逻辑状态时产生光脉冲。 该方法包括以下操作： - 在所述光学连接（16）上传输之前，在编码的数据序列（B（t））中编码（470,570）所述输入数据序列（b（t）），其中所述编码操作 使所述编码数据序列（B（t））中的第一逻辑状态（“1”）最小化。 优先应用于具有片上集成总线的光纤通信系统。

公开(公告)号：EP1524772A1

公开(公告)日：2005-04-20

申请号：EP03425662.8

申请日：2003-10-13

Applicant: STMicroelectronics S.r.l.

Inventor： Visalli, Giuseppe ,  Pappalardo, Francesco ,  Avellone, Giuseppe ,  Rimi, Francesco ,  Galluzzo, Agostino

IPC: H03M13/25 ,  H04L27/233

CPC classification number: H04L1/0059 ,  H03M13/256 ,  H04L1/0054 ,  H04L1/0068 ,  H04L25/067 ,  H04L27/2272 ,  H04L2027/0055 ,  H04L2027/0067

Abstract: A phase recovery and decoding method for decoding signals (S'(t)) comprising encoded symbols (u k ) over a respective symbol interval (T) which modulate a carrier, for example in a TCM system. The method envisages performing (20 to 26) a phase locking of the signal to be decoded so as to obtain a phase-locked signal which can present, during each symbol interval (T), variations induced by disturbances (noise, fading, etc.). The value attributed to the decoded symbol (U k ) is a function of the value assumed by the phase-locked signal on at least one subinterval of the symbol interval (T), for example located at the end of the symbol interval (T). Alternatively, the value assumed by the phase-locked signal on a plurality of subintervals comprised in each symbol interval (T) is detected (24,32), and a respective majority value of said phase-locked signal within said plurality of subintervals is identified (34,36). A suitable phase recovery and decoding circuit comprises a phase comparator (20), hard decision means (24), an encoder circuit (26), an oscillator (22) and a selection unit (28). For determining decoded value (U k ) and updating the state of the encoder circuit.

Abstract translation: 一种相位恢复和解码方法，用于在例如在TCM系统中调制载波的相应符号间隔（T）上对包括编码符号（uk）的信号（S'（t））进行解码。 该方法设想对待解码的信号执行（20至26）相位锁定，以获得在每个符号间隔（T）期间可能存在由干扰（噪声，衰落等）引起的变化的锁相信号。 ）。 归因于解码符号（Uk）的值是在符号间隔（T）的至少一个子间隔（例如位于符号间隔（T）的结尾）处由锁相信号假设的值的函数。 或者，检测包括在每个符号间隔（T）中的多个子间隔上的锁相信号所假设的值（24,32），并且识别所述多​​个子区间内的所述锁相信号的相应多数值 （34,36）。 合适的相位恢复和解码电路包括相位比较器（20），硬判决装置（24），编码器电路（26），振荡器（22）和选择单元（28）。 用于确定解码值（Uk）并更新编码器电路的状态。

公开(公告)号：EP1752872A2

公开(公告)日：2007-02-14

申请号：EP06116753.2

申请日：2006-07-06

Applicant: STMicroelectronics S.r.l.

Inventor： Visalli, Giuseppe ,  Pappalardo, Francesco

IPC: G06F7/74

CPC classification number: G06F7/74 ,  G06F7/485

Abstract: A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit operations with independent binary traffic for the operands. Preferably, this binary traffic is independent and equiprobable or quasi-equiprobable binary traffic, and the adder is a leading zero anticipatory logic integer adder producing a number having the same number of leading zeroes as the result of the integer addition performed. The carry value may be produced from a logic function (e.g., Karnaugh Map, Quine-McClusky) of the operands, as a logic combination of the operands covering all the 1s in the logic function.

Abstract translation: 用于从包括实际加法输入或至少一个较早载入的操作数开始的加法器中估计传播载波的电路，该电路用独立的二进制数据对操作数执行统计电路操作。 优选地，该二进制流量是独立的和等能的或准等能的二进制流量，并且加法器是前导零预期逻辑整数加法器，产生与执行的整数相加结果相同数量的前导零的数字。 进位值可以由操作数的逻辑功能（例如，Karnaugh Map，Quine-McClusky）产生，作为覆盖逻辑功能中的所有1的操作数的逻辑组合。

公开(公告)号：EP1717708A1

公开(公告)日：2006-11-02

申请号：EP05103593.9

申请日：2005-04-29

Applicant: STMicroelectronics S.r.l.

Inventor： Visalli, Giuseppe ,  Pappalardo, Francesco

IPC: G06F12/10

CPC classification number: G06F12/0895 ,  G06F12/1063 ,  Y02D10/13

Abstract: A cache memory system (115), comprising at least one cache memory (205) and a cache memory controller (210, Ft, Fd, 225, 230, 235, 245, 252). The at least one cache memory includes a plurality of storage locations (RLj), each one identified by a corresponding cache address (CADDR) and being adapted to store tag address portions (TAGi) and data words (DATi), each data word corresponding to a respective tag address portion. The cache memory controller is adapted to receive a first address (ADD) and to access the at least one cache memory based on the received first address.The cache memory controller includes a first address transformer (Ft, 225) adapted to receive the first address and to transform it into at least one first cache address corresponding thereto by applying a first transform function; the at least one first cache address is used by the cache memory controller for accessing the at least one cache memory to retrieve at least a first part of a tag address portion stored in at least one of the storage locations. The cache memory controller includes a hit detector (245) adapted to establish an at least partial hit condition based on a comparison of the retrieved at least a first part of the tag address portion and a first predetermined part (TAGp) of the first address, and a second address transformer (Fd, 225) adapted to receive the first address and to transform it into at least one second cache address corresponding thereto by applying a second transform function. The cache memory controller is further adapted to use the at least one second cache address for accessing the at least one cache memory to retrieve a data word corresponding to the retrieved tag address portion in case said at least partial hit condition is established.

Abstract translation: 一种高速缓冲存储器系统（115），包括至少一个高速缓冲存储器（205）和高速缓冲存储器控制器（210，Ft，Fd，225,230,235,245,252）。 所述至少一个高速缓存存储器包括多个存储位置（RLj），每个存储位置（RLj）由相应的高速缓存地址（CADDR）标识，并且适于存储标签地址部分（TAGi）和数据字（DATi），每个数据字对应于 相应的标签地址部分。 高速缓冲存储器控制器适于接收第一地址（ADD）并且基于接收的第一地址访问至少一个高速缓存存储器。高速缓存存储器控制器包括适于接收第一地址的第一地址变换器（Ft，225） 并通过应用第一变换函数将其变换成与之对应的至少一个第一高速缓存地址; 所述至少一个第一高速缓存地址被所述高速缓冲存储器控制器用于访问所述至少一个高速缓冲存储器以检索存储在至少一个所述存储位置中的标签地址部分的至少第一部分。 高速缓冲存储器控制器包括命中检测器（245），其适于基于检索到的标签地址部分的至少第一部分与第一地址的第一预定部分（TAGp）的比较建立至少部分命中条件， 以及适于接收第一地址并通过应用第二变换函数将其变换成与其对应的至少一个第二高速缓存地址的第二地址变换器（Fd，225）。 高速缓冲存储器控制器还适于在建立所述至少部分命中条件的情况下，使用至少一个第二高速缓存地址来访问所述至少一个高速缓存存储器以检索对应于所检索的标签地址部分的数据字。

公开(公告)号：EP1475906B1

公开(公告)日：2006-07-19

申请号：EP03010238.8

申请日：2003-05-07

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Francesco ,  Visalli, Giuseppe

IPC: H04B10/155 ,  H04L25/49

CPC classification number: H04L25/4908 ,  H04B10/524

公开(公告)号：EP1429239A3

公开(公告)日：2006-06-14

申请号：EP03027629.9

申请日：2003-12-02

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Francesco ,  Visalli, Giuseppe

IPC: G06F7/52 ,  G06F7/48

CPC classification number: G06F7/4876 ,  G06F7/483 ,  G06F7/49936 ,  G06F7/49947

Abstract: In a method for multiplication of floating-point real numbers (f, FN), encoded in a binary way in sign (SGN, SN), exponent (E, EN) and mantissa (M; MN), the multiplication of the mantissa (M; MN) envisages a step of calculation of partial products, which are constituted by a set of addenda (P) corresponding to said mantissa (MN). In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa (MN) to a value 1, in order to obtain a mantissa (MN) having a value comprised between 0.5 and 1.
Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point real numbers according to the IEEE754 standard.
Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.

Abstract translation: 在用符号（SGN，SN），指数（E，EN）和尾数（M; MN）二进制编码的浮点实数（f，FN）相乘的方法中，尾数 M; MN）设想了计算部分产品的步骤，所述部分产品由对应于所述尾数（MN）的一组附加部分（P）构成。 为了减小为计算而设计的电路的尺寸和功耗，采用二进制编码的方法，其设想将尾数（MN）的第一位设置为值1，以便获得尾数（MN） 具有在0.5和1之间的值。还提出了用于实现乘法方法的乘积和电路的四舍五入方法。 还示出了根据IEEE754标准的用于从浮点实数转换到浮点实数编码的电路。 优先应用在便携式和/或无线电子设备中，例如移动电话和PDA，具有低功耗要求。

公开(公告)号：EP1380961B1

公开(公告)日：2006-04-05

申请号：EP02425456.7

申请日：2002-07-10

Applicant: STMicroelectronics S.r.l.

Inventor： Visalli, Giuseppe ,  Pappalardo, Francesco

IPC: G06F13/42

CPC classification number: G06F13/4239

公开(公告)号：EP1429467A1

公开(公告)日：2004-06-16

申请号：EP03020851.6

申请日：2003-09-15

Applicant: STMicroelectronics S.r.l.

Inventor： Avellone, Giuseppe ,  Rimi, Francesco ,  Pappalardo, Francesco ,  Galluzzo, Agostino ,  Visalli, Giuseppe

IPC: H04B1/707

CPC classification number: H04B1/70735 ,  H04B1/7083

Abstract: Once slot synchronization has been obtained in a first step, during a second step there is acquired, by means of correlation (111, 117) of the received signal (r) with the synchronization codes, the information corresponding to the codegroup and to the fine slot synchronization. The synchronization codes are split into codesets. In a first step, a synchronization code identifying a corresponding codeset (CS) is identified by means of correlation (111) and search for the maximum value of correlation energy (114). In a second step, the received signal (r) is correlated (117) with the remaining codes (113) belonging to the codeset identified. The information thus obtained, which corresponds to all the synchronization codes comprised in the codeset identified, is used (115) for obtaining frame synchronization and codegroup identification. Preferential application is in mobile communication systems based upon standards, such as UMTS, CDMA2000, IS95 or WBCDMA.

Abstract translation: 一旦时隙同步已经在第一步骤中获得，在第二步骤期间出现被获取时，由所接收的信号（R）与所述同步码的相关性（111，117）的装置，所述信息对应于所述代码组和对细 时隙同步。 同步码被分成代码集。 在第一步骤中，一个同步码识别相应的代码组（CS）被识别BY相关（111）的方式，并搜索相关能量（114）的最大值。 在第二步骤中，接收到的信号（r）被相关（117）与属于所标识的代码组的剩余的代码（113）。 这样获得的信息，其对应于所标识的代码集包括的所有同步码，则使用（115），用于获得帧同步和码组识别。 优先应用是在基于标准的，：诸如UMTS，CDMA2000，IS95或WBCDMA码的移动通信系统。