Abstract:
A color image pixel data processing pipeline for performing, among corrective and image enhancement steps, at least an interpolation on color data to generate triplets located at distinct pixel locations, including among a plurality of defect correction and image enhancement blocks at least a first color interpolation block, generating RGB information for each pixel of the input image pixel pattern, a second color interpolation block receiving the RGB pattern pixels from said first color interpolation block and rendering enhanced RGB pattern pixels, and a plurality of dedicated line memories and delay circuits associated to and cooperating with said interpolation and correction blocks for permitting real-time processing of pixel data, further includes input image pixel pattern data read/write buffers first and second, of identical capacity suitable to store a subset or pixel block (m*n) of the image data, for translating the scanning mode of pixel data being fed to the input line memory and delay circuits associated to al least said first color interpolation block of said pipeline, from linewise to columnwise, for each subset of data stored in said first and second buffers. The switching from linewise writing to columnwise reading of the data temporarily stored in input buffer means, reduces overall memory requisite without sensibly increasing computational overhead.
Abstract:
A data stream (b(t)) including high ("1") and low ("0") logical states is transmitted over an optical link (16) by means of an optical source (15) adapted to be driven (14) via said the data stream to generate an optical signal for transmission over the optical link (16). The optical signal includes optical pulses generated at the occurrence of high logical ("1") states in said data stream (b(t)). The input data stream (b(t)) is coded (2000) into a coded data stream (B(t)) prior to the transmission over the optical link (16). The coding step minimises the logical high states ("1") in the coded data stream (B(t)), and the optical source (15) is driven by means of the coded data stream (B(t)) wherein the number of logical high states ("1") has been minimised.
Abstract:
In a method for multiplication of floating-point real numbers (f, FN), encoded in a binary way in sign (SGN, SN), exponent (E, EN) and mantissa (M; MN), the multiplication of the mantissa (M; MN) envisages a step of calculation of partial products, which are constituted by a set of addenda (P) corresponding to said mantissa (MN). In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa (MN) to a value 1, in order to obtain a mantissa (MN) having a value comprised between 0.5 and 1. Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point real numbers according to the IEEE754 standard. Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.
Abstract translation:在以二进制方式编码的符号(SGN,SN),指数(E,EN)和尾数(M; MN)的浮点实数(f,FN)的乘法方法中,尾数( M; MN)设想了由对应于所述尾数(MN)的一组附加(P)构成的部分乘积的计算步骤。 为了减小设计用于计算的电路的尺寸和功耗,采用了一种二进制编码方法,其设想将尾数(MN)的第一比特设置为值1,以获得尾数(MN) 具有包括在0.5和1之间的值。还提出了用于实现乘法的乘积和电路的舍入的方法。 还示出了根据IEEE754标准从浮点实数转换和编码的电路。 优先应用于便携式和/或无线电子设备,例如移动电话和PDA,具有低功耗要求。
Abstract:
To obtain frame synchronization and identify the cell codegroup in a cellular communication system (such as a system based upon the standard 3GPP FDD), there are available the synchronization codes (SSCH) organized in chips or letters transmitted at the beginning of respective slots. Slot synchronization is obtained previously in a first step of the operation of cell search. During a second step, there are acquired, by means of correlation (10) or fast Hadamard transform, the energy values corresponding to the respective individual letters with reference to the possible starting positions of the corresponding frame within the respective slot. Operating in a serial way (24) at the end of acquisition of the aforesaid energy values of the individual letters, or else operating in parallel, the energies of the corresponding words are determined. Of these eneriges only the maximum word-energy value and the information for the corresponding starting position are stored in a memory structure (22). Said maximum value and said starting position identify, respectively, the cell codes and the frame synchronization sought. A preferential application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95, or WBCDMA.
Abstract:
Processing method for forming an aggregate signal (y beam ) from a plurality of starting signals (x 1 , ... ,x 5 ), the method comprising the steps of: - acquiring said starting signals (x 1 , ... ,x 5 ) through respective sensors of a homogeneous sensors group (U 1 , ... ,U 5 ); - converting acquired signals in respective digital signals (x 1 , ... ,x 5 ) having data represented with a predetermined bits number; - processing the digital signals (x 1 , ... ,x 5 ) to form aggregate signal (y beam ). The processing step comprises the operations of: - modifying digital signals (x 1 , ... ,x 5 ) changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme (p 1 , ... ,p 5 ) associated with said data and to the specific digital signal comprising that data; - forming aggregate signal (y beam ) obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.