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    Amplitude and phase demodulator circuit for signals with very low modulation index
    11.
    发明公开
    Amplitude and phase demodulator circuit for signals with very low modulation index 失效
    调制信号调制器

    公开(公告)号：EP0892493A1

    公开(公告)日：1999-01-20

    申请号：EP97830363.4

    申请日：1997-07-18

    Applicant: STMicroelectronics S.r.l. ,  SIEMENS AKTIENGESELLSCHAFT

    Inventor： Poletto, Vanni ,  Sass, Dieter

    IPC: H03D1/22 ,  G06K7/08

    CPC classification number: G06K7/0008 ,  H03D3/002

    Abstract: An amplitude and phase demodulator circuit for signals with very low modulation index, comprising:

    amplifier means adapted to amplify a modulated signal (Vrx) coming from a transmitter (TX), said modulated signal being composed by a carrier and by a modulating component,
    characterized in that it further comprises means (13,24;10,11,27) adapted to cancel said carrier from said modulated signal (Vrx); said means adapted to cancel the carrier receiving in input the output signal (Va;Vb) of said amplifier means and a sync signal (SYNC) coming from said transmitter (TX), the output signal (Vout) of said amplifier means being delivered to receiver means (RX).

    Abstract translation: 一种用于具有非常低的调制指数的信号的振幅和相位解调器电路，包括：适于放大来自发射机（TX）的调制信号（Vrx）的放大器装置，所述调制信号由载波和调制分量组成， 其还包括适于从所述调制信号（Vrx）消除所述载波的装置（13,24; 10,11,27）; 所述装置适于在输入中抵消载波接收所述放大器装置的输出信号（Va; Vb）和来自所述发射机（TX）的同步信号（SYNC），所述放大器装置的输出信号（Vout）被传送到 接收机（RX）。

    Driving circuit for an electric load and system comprising the circuit
    12.
    发明公开
    Driving circuit for an electric load and system comprising the circuit 有权
    最后和系统解决器Schaltungsanordnung

    公开(公告)号：EP2280468A1

    公开(公告)日：2011-02-02

    申请号：EP10170644.8

    申请日：2010-07-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Amighini, Matteo ,  Poma, Alberto ,  Di Biase, Giuseppe ,  Poletto, Vanni

    IPC: H02H5/10 ,  H02M1/32

    CPC classification number: H02H5/10 ,  H02H7/12 ,  H02M3/156 ,  H02M2003/1555

    Abstract: An electronic circuit (100) is disclosed, comprising a node (EX), which connectable to a load (LD) to be driven and a power device (PD), which can be switched between activation and deactivation and having a first terminal connected to said node. The circuit further comprises:
    a current generator (I) having an output connected to said node and that can be enabled to generation, at least when the power device is deactivated;
    a comparator (CP) of an electric voltage of said node (V(EX)) with a reference voltage (V(REF)) configured to obtain comparison signals (RESETN), from which distinct conditions of electric connection of the load to said node will be detected.

    Abstract translation: 公开了一种电子电路（100），其包括可连接到待驱动的负载（LD）和功率器件（PD）的节点（EX），其可以在激活和去激活之间切换，并且具有连接到 说节点。 所述电路还包括：电流发生器（I），其具有连接到所述节点的输出，并且至少当所述功率器件被去激活时，所述电流发生器（I）能够被产生; 配置为具有参考电压（V（REF））的所述节点（V（EX））的电压的比较器（CP），以获得比较信号（RESETN），从而从负载到所述节点的电连接的不同条件 将被检测到。

    PULSE WIDTH MODULATION DECODER CIRCUIT, CORRESPONDING DEVICE AND METHODS OF OPERATION
    19.
    发明公开
    PULSE WIDTH MODULATION DECODER CIRCUIT, CORRESPONDING DEVICE AND METHODS OF OPERATION 审中-公开

    公开(公告)号：EP4020815A1

    公开(公告)日：2022-06-29

    申请号：EP21214636.9

    申请日：2021-12-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： Poletto, Vanni ,  Floriani, Ivan

    IPC: H03M1/50 ,  H03K7/08 ,  H03K9/08

    Abstract: A circuit (20A) for decoding a pulse width modulated signal ( PWM ) comprises an input node (200) configured to receive the pulse width modulated signal ( PWM ) , and an output node (202) configured to provide an output signal ( DATA ) switching between a first output value and a second output value as a function of the duty-cycle of the input pulse width modulated signal ( PWM ) . A current generating circuitry (22) is coupled between a supply voltage node ( V dd ) and a ground voltage node (GND) . The current generating circuitry is coupled to the input node (200) to receive the input pulse width modulated signal ( PWM ) and is coupled to an intermediate node (204) of the circuit to inject a current ( I H ) therein or to sink a current ( I L ) therefrom as a function of the value of the input pulse width modulated signal ( PWM ) . A capacitance (C) has a first terminal coupled to the intermediate node (204), and it is alternatively charged and discharged by the currents ( I H , I L ) generated by the current generating circuitry (22). A comparator circuit (24) is coupled between the intermediate node (204) and the output node (202). The comparator circuit (24) is configured to sense a voltage signal (Vc) at the intermediate node (204), compare the sensed voltage signal (Vc) to a reference voltage signal ( V ref ), and drive the output node (202) to the first output value or to the second output value as a function of the comparison, thereby generating the output signal ( DATA ) .

    Method and apparatus for decoding Manchester-encoded signals
    20.
    发明公开
    Method and apparatus for decoding Manchester-encoded signals 有权
    Verfahren und Vorrichtung zur Dekodierung Manchester-kodierter Signale

    公开(公告)号：EP1347609A1

    公开(公告)日：2003-09-24

    申请号：EP02425178.7

    申请日：2002-03-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Poletto, Vanni ,  Ghigini, Paolo

    IPC: H04L25/49 ,  H03M5/14

    CPC classification number: H03M5/12 ,  H04L25/4904

    Abstract: Method and decoder for decoding a Manchester encoded binary data signal (RX_DATA). The decoding method comprises the following steps:

    receiving the binary data signal (RX_DATA) comprising a first sequence of bit central transitions (40) and a second sequence of bit initial transitions (42),
    generating a local clock signal (CK), and
    determining the central transitions (40) of said encoded binary data signal (RX_DATA),
       and is characterized in that the central transition (40) determination step comprises the following steps:

    measuring, by means of the local clock signal (CK), the time interval elapsing between a pair adjacent central transitions (40), expressed as a number N of cycles of the local clock signal (CK),
    selecting each successive central transition (40) on the basis of the time interval N measured between the pair of central transitions (40) which immediately precede said successive central transition (40).

    Abstract translation: 用于解码曼彻斯特编码二进制数据信号（RX_DATA）的方法和解码器。 解码方法包括以下步骤：接收包含第一比特中心转换序列（40）和第二比特初始转换序列（42）的二进制数据信号（RX_DATA），产生本地时钟信号（CK），并确定 所述编码二进制数据信号（RX_DATA）的中心转换（40），其特征在于中央转移（40）确定步骤包括以下步骤：通过本地时钟信号（CK）测量时间间隔 通过表示为本地时钟信号（CK）的周期数N的一对相邻的中心转换（40）之间经过，基于在一对中央转换之间测量的时间间隔N来选择每个连续的中心转换（40） （40），其紧接在所述连续中心转换（40）之前。

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