中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.026 seconds)

    Driving circuit for an electric load and system comprising the circuit
    2.
    发明公开
    Driving circuit for an electric load and system comprising the circuit 有权
    最后和系统解决器Schaltungsanordnung

    公开(公告)号：EP2280468A1

    公开(公告)日：2011-02-02

    申请号：EP10170644.8

    申请日：2010-07-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Amighini, Matteo ,  Poma, Alberto ,  Di Biase, Giuseppe ,  Poletto, Vanni

    IPC: H02H5/10 ,  H02M1/32

    CPC classification number: H02H5/10 ,  H02H7/12 ,  H02M3/156 ,  H02M2003/1555

    Abstract: An electronic circuit (100) is disclosed, comprising a node (EX), which connectable to a load (LD) to be driven and a power device (PD), which can be switched between activation and deactivation and having a first terminal connected to said node. The circuit further comprises:
    a current generator (I) having an output connected to said node and that can be enabled to generation, at least when the power device is deactivated;
    a comparator (CP) of an electric voltage of said node (V(EX)) with a reference voltage (V(REF)) configured to obtain comparison signals (RESETN), from which distinct conditions of electric connection of the load to said node will be detected.

    Abstract translation: 公开了一种电子电路（100），其包括可连接到待驱动的负载（LD）和功率器件（PD）的节点（EX），其可以在激活和去激活之间切换，并且具有连接到 说节点。 所述电路还包括：电流发生器（I），其具有连接到所述节点的输出，并且至少当所述功率器件被去激活时，所述电流发生器（I）能够被产生; 配置为具有参考电压（V（REF））的所述节点（V（EX））的电压的比较器（CP），以获得比较信号（RESETN），从而从负载到所述节点的电连接的不同条件 将被检测到。

    Rail to rail rectifying integrator
    3.
    发明公开
    Rail to rail rectifying integrator 有权
    积分器具有整流功能，并且具有相应的输出电压范围的电源电压

    公开(公告)号：EP1176721A1

    公开(公告)日：2002-01-30

    申请号：EP00830521.1

    申请日：2000-07-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pernigotti, Elena ,  Poma, Alberto ,  Protti, Carlo

    IPC: H03K5/1532 ,  G01R19/04

    CPC classification number: G01R19/04

    Abstract: A rectifying integrator of an input signal (VIN) with full output dynamic, relative to a voltage reference (VREF) intermediate in respect to the dynamic of the input signal (VIN), the line of integration of which is composed of an integrator of that portion of the input signal that exceeds the voltage reference (VREF) and of a hold capacitor (C 3a ) coupled in cascade to the integrator, includes a second line of integration, identical to the first line of integration, that integrates that portion of the input signal (VIN) that remains below the voltage reference (VREF), and an adder output stage that generates an output signal (VOUT) equal to the difference between the voltages existing on the hold capacitors (C 3a , C 3b ) of the lines of integration first and second.

    Abstract translation: 与所述输入信号（VIN），它是由做的积分的所有一体化的线的动态满输出动态，相对于基准电压（VREF）中间体在相对于输入信号（VIN）的整流积分 在输入信号的各部分没有超过参考电压（VREF）和级联耦合到积分器的保持电容器（C 3a）中的，包括集成的第二线，相同的整合的第一行，没有集成做了输入的部 该保持低于参考电压（VREF），且在加法器输出级信号（VIN）确实产生等于存在于集成的线的保持电容（C3a的，的C3b）第一电压之间的差输出信号的速率（VOUT） 和第二。

Patent Agency Ranking