公开(公告)号：EP1223483A1

公开(公告)日：2002-07-17

申请号：EP01130837.6

申请日：2001-12-27

Applicant: STMicroelectronics S.r.l.

Inventor： Poletto, Vanni

IPC: G05B11/42

CPC classification number: G05B11/42

Abstract: The present invention relates to a digital control circuit of the P.I. (Proportional Integral) type, receiving an error signal (Error) at an input terminal (IN1) and adapted to provide, at an output terminal (OUT1), a PWM [Pulse Width Modulated] output signal (PWM Output). The circuit is of a type which comprises at least one analog-to-digital converter (100, 100*) connected to the input terminal (IN) and to the output terminal (OUT1) through at least one integrative/proportional branch (120, 121, 130, 134).
Advantageously in this invention, the analog-to-digital converter (100, 100*) is an integration converter adapted to integrate the error signal (Error) before an analog-to-digital conversion thereof.

Abstract translation: 本发明涉及一种P.I.的数字控制电路。 （比例积分）类型，在输入端（IN1）处接收错误信号（Error），并适于在输出端（OUT1）处提供PWMÄ脉冲宽度调制的输出信号（PWM输出）。 该电路是包括通过至少一个积分/比例分支（120,150）连接到输入端（IN）和至输出端（OUT1）的至少一个模拟数字转换器（100,100 *）的类型， 121，130，134）。 在本发明中有利的是，模数转换器（100,100 *）是适用于在其模数转换之前对误差信号（误差）进行积分的积分转换器。

公开(公告)号：EP1347609B1

公开(公告)日：2007-11-21

申请号：EP02425178.7

申请日：2002-03-22

Applicant: STMicroelectronics S.r.l.

Inventor： Poletto, Vanni ,  Ghigini, Paolo

IPC: H04L25/49 ,  H03M5/14

CPC classification number: H03M5/12 ,  H04L25/4904

公开(公告)号：EP0949736B1

公开(公告)日：2004-03-17

申请号：EP98830221.2

申请日：1998-04-10

Applicant: STMicroelectronics S.r.l.

Inventor： Crespi, Angelo ,  Poletto, Vanni

IPC: H02H7/122

CPC classification number: H02H7/1222

公开(公告)号：EP1223483B1

公开(公告)日：2004-03-03

申请号：EP01130837.6

申请日：2001-12-27

Applicant: STMicroelectronics S.r.l.

Inventor： Poletto, Vanni

IPC: G05B11/42

CPC classification number: G05B11/42

公开(公告)号：EP1113254A1

公开(公告)日：2001-07-04

申请号：EP99830814.2

申请日：1999-12-30

Applicant: STMicroelectronics S.r.l. ,  MAGNETI MARELLI S.p.A.

Inventor： Mazzucco, Michelangelo ,  Poletto, Vanni ,  Protti, Melano Carlo Lorenzo

IPC: G01L23/22 ,  G06J1/00

CPC classification number: G01L23/225 ,  G06J1/00

Abstract: A circuit and a method are described for extending the output voltage range of an integrator circuit (22) wherein the input signal (V r ) is such as to produce an output signal (V o ) the voltage of which develops monotonically within a predetermined range of possible values.
The integrator circuit (22) is driven in a manner such that, within an integration time period (T i ), each time the signal (V o ) at its output reaches a limit of the range of values, the integrator circuit (22) starts a subsequent integration stage of the input signal (V r ) in which the output signal (V o ) develops again within the above-mentioned range. This takes place by resetting of the integrator circuit (22) or by reversal of the characteristic slope of the output signal (V o ).
The actual voltage value (V out ) of the signal is calculated from the counting of the reset pulses.

Abstract translation: 描述了用于扩展积分器电路（22）的输出电压范围的电路和方法，其中输入信号（Vr）产生其电压在可能的预定范围内单调呈现的输出信号（Vo） 值。 积分器电路（22）以这样的方式驱动，使得在积分时间段（Ti）内，每当其输出端的信号（Vo）达到值范围的极限时，积分器电路22将启动 输出信号（Vr）的后续积分级，其中输出信号（Vo）再次产生在上述范围内。 这通过复位积分器电路（22）或通过反转输出信号（Vo）的特性斜率来进行。 信号的实际电压值（Vout）由复位脉冲的计数来计算。

公开(公告)号：EP1052518A1

公开(公告)日：2000-11-15

申请号：EP99830294.7

申请日：1999-05-13

Applicant: STMicroelectronics S.r.l. ,  MAGNETI MARELLI S.p.A.

Inventor： Milanesi, Andrea ,  Chicca, Stefania ,  Poletto, Vanni ,  Giorgetta, Valerio ,  Sgatti, Stefano ,  Vigna, Sergio

IPC: G01R31/02

CPC classification number: G01R31/024

Abstract: A system is described for the diagnosis of a driver (D) of the type adapted to detect one or more circuit anomalies which can occur in the said driver, including:

voltage comparator circuits (10, 20) adapted to generate diagnostic logic signals (F 1 , F 2 , F 3 ) each indicative of the existence of a corresponding type of anomaly; and
a coding circuit (M, SM) adapted to receive these diagnostic signals (F 1 , F 2 , F 3 ) and to output information relating to an overall operating state of the circuit. The coding circuit (M, SM) includes a first portion adapted to provide at its output first logic signals (SHB, SHG, OL) indicative of the last anomaly occurred since a system reset operation, and a second portion for coding such first logic signals (SHB, SHG, OL). The second portion includes a sequential logic network (SM) adapted to:


receive the first logic input signals (SHB, SHG, OL) and at least one second logic signal (IN) indicative of the current operating phase of the driver (D); and
achieve, as a function of the said first and second logic signals (SHB, SHG, OL; IN) a stable internal state such as to determine at the output information in the form of an N bit coded word representative of an occurred anomaly, of a condition of absence of anomaly in the current operating phase, or of a condition of absence of anomaly in any operating phase.

Abstract translation: 描述了用于诊断适于检测可能发生在所述驱动器中的一个或多个电路异常的类型的驱动器（D）的系统，包括：适于产生诊断逻辑信号的电压比较器电路（10,20）（F1 ，F2，F3），每个指示存在相应类型的异常; 以及适于接收这些诊断信号（F1，F2，F3）的编码电路（M，SM），并且输出与电路的总体工作状态有关的信息。 编码电路（M，SM）包括适于在其输出端提供指示自系统复位操作以来发生的最后异常的第一逻辑信号（SHB，SHG，OL）的第一部分和用于对这些第一逻辑信号进行编码的第二部分 （SHB，SHG，OL）。 第二部分包括适于：接收第一逻辑输入信号（SHB，SHG，OL）的顺序逻辑网络（SM）和指示驾驶员（D）的当前操作阶段的至少一个第二逻辑信号（IN）; 并且作为所述第一和第二逻辑信号（SHB，SHG，OL; IN）的函数实现稳定的内部状态，例如以表示发生的异常的N位编码字的形式在输出信息处确定， 在当前运行阶段没有异常的情况，或任何运行阶段没有异常的情况。

公开(公告)号：EP0959560A1

公开(公告)日：1999-11-24

申请号：EP98830318.6

申请日：1998-05-22

Applicant: STMicroelectronics S.r.l.

Inventor： Milanesi, Andrea ,  Poletto, Vanni

IPC: H03F3/45

CPC classification number: H03F3/45479

Abstract: A differential amplifier with an outstandingly high common mode rejection and full input dynamic employs a comparator, to the inputs of which are applied the two input signals for outputting a signal whose sign is indicative of the sign of the difference between the two input signals. The operational amplifier of the basic diagram of the differential amplifier is fedback through a current mirror and the feedback signal is switchingly applied to the non inverting input or to the inverting input of the operational amplifier, depending on the sign of the difference detected by the comparator, thus ensuring in any case a negative feedback. To this end, in cascade to the output of the operational amplifier, there is also a stage whose function is to invert or not the sign of the output signal of the operational amplifier, depending on the sign information provided by the comparator. Whether inverted or not, the output signal drives an output stage consisting of a transistor and a resistive load, the value of which may be designed to define a certain multiplying factor of the difference between the input signals and constituting the input branch of a current mirror that, through a switch controlled by the output of the comparator, injects a feedback current either on the inverting or on the non inverting input node of the operational amplifier.

Abstract translation: 具有非常高的共模抑制和全输入动态的差分放大器采用比较器，其输入端被施加两个输入信号，用于输出其符号表示两个输入信号之间的差的符号的信号。 差分放大器的基本图的运算放大器通过电流镜反馈，反馈信号根据由比较器检测到的差异的符号切换到运算放大器的非反相输入或反相输入端 ，从而确保在任何情况下的负面反馈。 为此，级联到运算放大器的输出，还有一个阶段，其功能是根据比较器提供的符号信息来反转或不反转运算放大器的输出信号的符号。 无论是否反相，输出信号驱动由晶体管和电阻负载组成的输出级，其值可被设计为定义输入信号之间的差异的一定倍数，并构成电流镜的输入支路 通过由比较器的输出控制的开关，在运算放大器的反相或非反相输入节点上注入反馈电流。

公开(公告)号：EP0954079A1

公开(公告)日：1999-11-03

申请号：EP98830252.7

申请日：1998-04-27

Applicant: STMicroelectronics S.r.l.

Inventor： Milanesi, Andrea ,  Chicca, Stefania ,  Morelli, Marco ,  Poletto, Vanni

IPC: H02H1/00 ,  G01R31/00 ,  H03K17/082

CPC classification number: H03K17/0822

Abstract: A guard circuit of a diagnostic output line (K-line) of a control unit (ECU) in the event of a ground (GND) disconnection or of a "below ground" condition, where the diagnostic output line (K-line) comprises a first interface DMOS transistor (MI) with a source connected to ground and a drain coupled to the diagnostic output lines (VOUT) through a second DMOS transistor (MP) with a source connected to the output line (VOUT) and a drain connected to the source of the first DMOS transistor (MI), a comparator (COMP) of the voltage (VOUT) of the diagnostic output line with the potential of the ground node (GND), a two-input logic (AND) gate (A1), with an input connected to the output of the comparator (COMP) and the other input coupled to the gate of said first DMOS transistor (MI), whose output controls a current generator (I) forcing a current, limited by a resistor (R), on the diagnostic output line (VOUT), the gate of the second DMOS transistor (MP) being coupled to the connection node between the generator (I) and the limiting resistor (R), employs a third MOS transistor (M) for switching off the second DMOS transistor (MP), functionally coupled in parallel to the resistor (R) and controlled by a line comprising a second current generator (I 1 ) controlled through an inverter (INV) by the output of the comparator (COMP) and forcing a current through a voltage divider (R 1 , R 2 ) on said diagnostic output line (VOUT). The intermediate node of the voltage divider is coupled to a gate of the third MOS transistor (M), and a third current generator (I 2 ) connected between the gate of the third transistor (M) and ground is controlled by the output of the comparator (COMP) in phase to the first current generator (I) and in phase opposition to the second current generator (I 1 ).

Abstract translation: 在诊断输出线（K线）包括地面（GND）断开或“低于地面”状态的情况下，控制单元（ECU）的诊断输出线（K线）的保护电路 源极连接到地的第一接口DMOS晶体管（MI）和通过连接到输出线（VOUT）的源极的第二DMOS晶体管（MP）耦合到诊断输出线（VOUT）的漏极，以及漏极连接到 第一DMOS晶体管（MI）的源极，具有接地节点（GND）的电位的诊断输出线的电压（VOUT）的比较器（COMP），双输入逻辑（AND）门（A1） ，其中输入连接到比较器（COMP）的输出端，而另一个输入端耦合到所述第一DMOS晶体管（MI）的栅极，其输出控制电流发生器（I），该电流发生器（I）由电阻器（R ），在诊断输出线（VOUT）上，第二DMOS晶体管（MP）的栅极耦合到连接节点 在发生器（I）和限制电阻器（R）之间使用用于关断第二DMOS晶体管（MP）的第三MOS晶体管（M），其功能上与电阻器（R）并联并且由包括 通过比较器（COMP）的输出通过反相器（INV）控制第二电流发生器（I1），并强制通过所述诊断输出线（VOUT）上的分压器（R1，R2）的电流。 分压器的中间节点耦合到第三MOS晶体管（M）的栅极，并且连接在第三晶体管（M）的栅极与地之间的第三电流发生器（I2）由比较器的输出端控制 （COMP）与第一电流发生器（I）同相并且与第二电流发生器（I1）相反。

公开(公告)号：EP0892493A1

公开(公告)日：1999-01-20

申请号：EP97830363.4

申请日：1997-07-18

Applicant: STMicroelectronics S.r.l. ,  SIEMENS AKTIENGESELLSCHAFT

Inventor： Poletto, Vanni ,  Sass, Dieter

IPC: H03D1/22 ,  G06K7/08

CPC classification number: G06K7/0008 ,  H03D3/002

Abstract: An amplitude and phase demodulator circuit for signals with very low modulation index, comprising:

amplifier means adapted to amplify a modulated signal (Vrx) coming from a transmitter (TX), said modulated signal being composed by a carrier and by a modulating component,
characterized in that it further comprises means (13,24;10,11,27) adapted to cancel said carrier from said modulated signal (Vrx); said means adapted to cancel the carrier receiving in input the output signal (Va;Vb) of said amplifier means and a sync signal (SYNC) coming from said transmitter (TX), the output signal (Vout) of said amplifier means being delivered to receiver means (RX).

Abstract translation: 一种用于具有非常低的调制指数的信号的振幅和相位解调器电路，包括：适于放大来自发射机（TX）的调制信号（Vrx）的放大器装置，所述调制信号由载波和调制分量组成， 其还包括适于从所述调制信号（Vrx）消除所述载波的装置（13,24; 10,11,27）; 所述装置适于在输入中抵消载波接收所述放大器装置的输出信号（Va; Vb）和来自所述发射机（TX）的同步信号（SYNC），所述放大器装置的输出信号（Vout）被传送到 接收机（RX）。

公开(公告)号：EP2280468A1

公开(公告)日：2011-02-02

申请号：EP10170644.8

申请日：2010-07-23

Applicant: STMicroelectronics S.r.l.

Inventor： Amighini, Matteo ,  Poma, Alberto ,  Di Biase, Giuseppe ,  Poletto, Vanni

IPC: H02H5/10 ,  H02M1/32

CPC classification number: H02H5/10 ,  H02H7/12 ,  H02M3/156 ,  H02M2003/1555

Abstract: An electronic circuit (100) is disclosed, comprising a node (EX), which connectable to a load (LD) to be driven and a power device (PD), which can be switched between activation and deactivation and having a first terminal connected to said node. The circuit further comprises:
a current generator (I) having an output connected to said node and that can be enabled to generation, at least when the power device is deactivated;
a comparator (CP) of an electric voltage of said node (V(EX)) with a reference voltage (V(REF)) configured to obtain comparison signals (RESETN), from which distinct conditions of electric connection of the load to said node will be detected.

Abstract translation: 公开了一种电子电路（100），其包括可连接到待驱动的负载（LD）和功率器件（PD）的节点（EX），其可以在激活和去激活之间切换，并且具有连接到 说节点。 所述电路还包括：电流发生器（I），其具有连接到所述节点的输出，并且至少当所述功率器件被去激活时，所述电流发生器（I）能够被产生; 配置为具有参考电压（V（REF））的所述节点（V（EX））的电压的比较器（CP），以获得比较信号（RESETN），从而从负载到所述节点的电连接的不同条件 将被检测到。