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    LAYER STRUCTURE INCLUDING DIFFUSION BARRIER LAYER AND METHOD OF MANUFACTURING THE SAME
    11.
    发明申请
    LAYER STRUCTURE INCLUDING DIFFUSION BARRIER LAYER AND METHOD OF MANUFACTURING THE SAME 审中-公开
    包括扩散障碍层的层结构及其制造方法

    公开(公告)号：US20160240482A1

    公开(公告)日：2016-08-18

    申请号：US14814938

    申请日：2015-07-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunjae SONG ,  Seunggeol NAM ,  Yeonchoo CHO ,  Seongjun PARK ,  Hyeonjin SHIN ,  Jaeho LEE

    IPC: H01L23/532 ,  H01L21/768

    CPC classification number: H01L23/53209 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/5226

    Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

    Abstract translation: 示例实施例涉及具有扩散阻挡层的层结构及其制造方法。 层结构包括第一和第二材料层以及它们之间的扩散阻挡层。 扩散阻挡层包括纳米晶石墨烯（nc-G）层。 在层结构中，扩散阻挡层还可以与nc-G层一起包括非石墨烯金属化合物层或石墨烯层。 第一和第二材料层之一是绝缘层，金属层或半导体层，其余层可以是金属层。

    METHOD FOR PROVIDING SEARCH KEYWORD AND ELECTRONIC DEVICE SUPPORTING THE SAME
    13.
    发明申请
    METHOD FOR PROVIDING SEARCH KEYWORD AND ELECTRONIC DEVICE SUPPORTING THE SAME 审中-公开
    提供搜索关键字的方法和支持相同的电子设备

    公开(公告)号：US20160103847A1

    公开(公告)日：2016-04-14

    申请号：US14882718

    申请日：2015-10-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiwoo LEE ,  Sunghyun KYUNG ,  Jaeho LEE

    IPC: G06F17/30

    CPC classification number: G06F16/9537 ,  G06F16/3326 ,  G06F16/338

    Abstract: A method for providing a search keyword and an electronic device supporting the same is provided. The method for providing, by an electronic device, a search keyword, the method includes displaying search results comprising at least one item in response to an entry of a first search keyword into a search keyword entry region, determining continuity between the first search keyword and a second search keyword which is a search keyword entered prior to the first search keyword, and storing at least one of the first search keyword and a search formula, in which the first search keyword and the second search keyword have been combined in a search keyword list, in response to the determination of the continuity between the first search keyword and the second search keyword.

    Abstract translation: 提供了一种用于提供搜索关键字的方法和支持其的电子设备。 用于通过电子设备提供搜索关键字的方法包括：响应于第一搜索关键字的入口响应于搜索关键词进入区域显示包括至少一个项目的搜索结果，确定第一搜索关键字和 第二搜索关键字，其是在第一搜索关键字之前输入的搜索关键字，并且将搜索关键字和搜索关键字中的第一搜索关键字和第二搜索关键词组合在搜索关键字中的至少一个中存储 响应于确定第一搜索关键字和第二搜索关键字之间的连续性的列表。

    NEUROMORPHIC METHOD AND APPARATUS WITH MULTI-BIT NEUROMORPHIC OPERATION
    14.
    发明公开
    NEUROMORPHIC METHOD AND APPARATUS WITH MULTI-BIT NEUROMORPHIC OPERATION 审中-公开

    公开(公告)号：US20240086694A1

    公开(公告)日：2024-03-14

    申请号：US18508519

    申请日：2023-11-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungho Kim ,  Cheheung KIM ,  Jaeho LEE

    IPC: G06N3/063 ,  G06F7/501 ,  G06F7/523 ,  G11C11/54

    CPC classification number: G06N3/063 ,  G06F7/501 ,  G06F7/523 ,  G11C11/54

    Abstract: A neuromorphic apparatus configured to process a multi-bit neuromorphic operation including a single axon circuit, a single synaptic circuit, a single neuron circuit, and a controller. The single axon circuit is configured to receive, as a first input, an i-th bit of an n-bit axon. The single synaptic circuit is configured to store, as a second input, a j-th bit of an m-bit synaptic weight and output a synaptic operation value between the first input and the second input. The single neuron circuit is configured to obtain each bit value of a multi-bit neuromorphic operation result between the n-bit axon and the m-bit synaptic weight, based on the output synaptic operation value. The controller is configured to respectively determine the i-th bit and the j-th bit to be sequentially assigned for each time period of different time periods to the single axon circuit and the single synaptic circuit.

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