公开(公告)号：US20220392886A1

公开(公告)日：2022-12-08

申请号：US17887758

申请日：2022-08-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann EDWARDS ,  Akram A. SALMAN ,  Binghua Hu

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L21/763 ,  H01L21/762 ,  H01L21/8222

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

公开(公告)号：US20130207211A1

公开(公告)日：2013-08-15

申请号：US13768024

申请日：2013-02-15

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann EDWARDS ,  Dimitar Trifonov TRIFONOV

IPC: H01L31/02

CPC classification number: H01L31/02002 ,  H01L31/022408 ,  H01L31/1013 ,  H01L31/103

Abstract: A semiconductor device contains a photodiode which has a plurality of p-n junctions disposed in a stack. Two contact structures on the semiconductor device are connected across at least one of the junctions to allow electrical connection to an external detection circuit, so that signal current from incident light on the photodiode which generates electron-hole pairs across the connected junction may be sensed by the external detection circuit. At least one of the junctions is electrically shorted at the semiconductor device, so that signal current from the shorted junction may not be sensed by the external detection circuit.

Abstract translation: 半导体器件包含具有布置在堆叠中的多个p-n结的光电二极管。 半导体器件上的两个接触结构连接在至少一个结点上，以允许与外部检测电路的电连接，从而在穿过连接的接合点产生电子 - 空穴对的光电二极管上的入射光的信号电流可以被 外部检测电路。 至少一个结点在半导体器件处电气短路，使得来自短路端的信号电流可能不被外部检测电路感测到。

公开(公告)号：US20130207210A1

公开(公告)日：2013-08-15

申请号：US13767978

申请日：2013-02-15

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann EDWARDS ,  Dimitar Trifonov TRIFONOV

IPC: H01L31/075 ,  H01L31/0224

CPC classification number: H01L31/075 ,  H01L31/0224 ,  H01L31/022408 ,  H01L31/103 ,  H01L31/1804 ,  Y02E10/547

Abstract: A semiconductor device contains a photodiode which includes a buried collection region formed by a bandgap well to vertically confine photo-generated minority carriers. the bandgap well has the same conductivity as the semiconductor material immediately above and below the bandgap well. A net average doping density in the bandgap well is at least a factor of ten less than net average doping densities immediately above and below the bandgap well. A node of the photodiode, either the anode or the cathode, is connected to the buried collection region to collect the minority carriers, the polarity of the node matches the polarity of the minority carriers. The photodiode node connected to the buried collection region occupies less lateral area than the lateral area of the buried collection region.

Abstract translation: 半导体器件包括光电二极管，其包括由带隙阱形成的掩埋采集区域，以垂直地限制光产生的少数载流子。 带隙阱具有与带隙阱正上方和下方的半导体材料相同的导电性。 带隙阱中的净平均掺杂密度至少比带隙阱上方和下方的净平均掺杂密度小十倍。 光电二极管（阳极或阴极）的一个节点连接到埋藏采集区域以收集少数载流子，节点的极性与少数载流子的极性匹配。 连接到埋藏采集区的光电二极管节点占据比埋藏收集区域的侧向区域更小的横向面积。

公开(公告)号：US20240105840A1

公开(公告)日：2024-03-28

申请号：US18528057

申请日：2023-12-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann EDWARDS

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7824 ,  H01L29/0852 ,  H01L29/1033 ,  H01L29/66681

Abstract: A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.

公开(公告)号：US20220352406A1

公开(公告)日：2022-11-03

申请号：US17246068

申请日：2021-04-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rahmi HEZAR ,  Henry Litzmann EDWARDS

IPC: H01L31/107 ,  H01L31/02 ,  H01L31/109

Abstract: An integrated circuit includes a photodetector that has an epitaxial layer with a first conductivity type located over a substrate. A buried layer of the first conductivity type is located within the epitaxial layer and has a higher carrier concentration than the epitaxial layer. A semiconductor layer located over the buried layer has an opposite second conductivity type and includes a first sublayer over the buried semiconductor layer and a second sublayer between the first sublayer and the buried layer. The first sublayer has a larger lateral dimension than the second sublayer, and has a lower carrier concentration than the second sublayer.

公开(公告)号：US20220209007A1

公开(公告)日：2022-06-30

申请号：US17136816

申请日：2020-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Boguslaw KOCON ,  Henry Litzmann EDWARDS

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  H01L29/45

Abstract: A semiconductor device includes a switch element having a surface and first and second regions and including a first semiconductor material having a band-gap. The first region of the switch element is coupled to a source contact. A floating electrode has first and second ends. The first end of the floating electrode is coupled to the second region of the switch element. A voltage-support structure includes a second semiconductor material having a band-gap that is larger than the band-gap of the first semiconductor material. The voltage-support structure is in contact with the second end of the floating electrode. A drain contact is coupled to the voltage-support structure.

公开(公告)号：US20220199611A1

公开(公告)日：2022-06-23

申请号：US17129495

申请日：2020-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Zaichen CHEN ,  Akram Ali SALMAN ,  Henry Litzmann EDWARDS

IPC: H01L27/02 ,  H01L29/06 ,  H01L21/8249

Abstract: In an example, an electronic device includes a first well having a first conductivity type within a semiconductor substrate and a second well having a second opposite conductivity type within the semiconductor substrate and touching the first well. The device further includes a third well having the first conductivity type within the second well. A metallic structure in direct contact with at least a portion of a surface of the third well thereby forms a Schottky barrier between the third well and the metallic structure.

公开(公告)号：US20200303518A1

公开(公告)日：2020-09-24

申请号：US16897382

申请日：2020-06-10

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann EDWARDS ,  Andrew D. STRACHAN

IPC: H01L29/66 ,  H01L21/266 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/40

Abstract: A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.

公开(公告)号：US20190148517A1

公开(公告)日：2019-05-16

申请号：US15813934

申请日：2017-11-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann EDWARDS ,  Andrew D. STRACHAN

IPC: H01L29/66 ,  H01L21/266 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78

Abstract: A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.

公开(公告)号：US20180175021A1

公开(公告)日：2018-06-21

申请号：US15895694

申请日：2018-02-13

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann EDWARDS ,  Akram A. SALMAN ,  Binghua HU

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8222 ,  H01L21/265 ,  H01L21/763 ,  H01L21/762 ,  H01L27/06

CPC classification number: H01L27/0259 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/762 ,  H01L21/76237 ,  H01L21/763 ,  H01L21/8222 ,  H01L27/0623 ,  H01L29/06 ,  H01L29/0692 ,  H01L29/10 ,  H01L29/1095

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.