公开(公告)号：US11869986B2

公开(公告)日：2024-01-09

申请号：US17459991

申请日：2021-08-27

Applicant: Texas Instruments Incorporated

Inventor： Umamaheswari Aghoram ,  Akram Ali Salman ,  Binghua Hu ,  Alexei Sadovnikov

IPC: H01L29/866 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L29/866 ,  H01L27/0255 ,  H01L29/66106 ,  H01L27/0259

Abstract: A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.

公开(公告)号：US11121207B2

公开(公告)日：2021-09-14

申请号：US15348459

申请日：2016-11-10

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Abbas Ali ,  Sopa Chevacharoenkul ,  Jarvis Benjamin Jacobs

IPC: H01L49/02 ,  H01L21/762 ,  H01L21/265 ,  H01L21/308

Abstract: A method for forming trench capacitors includes forming a silicon nitride layer over a first region of a semiconductor surface doped a first type and over a second region doped a second type. A patterned photoresist layer is directly formed on the silicon nitride layer. An etch forms a plurality of deep trenches (DTs) within the first region. A liner oxide is formed that lines the DTs. The silicon nitride layer is etched forming an opening through the silicon nitride layer that is at least as large in area as the area of an opening in the semiconductor surface of the DT below the silicon nitride layer. The liner oxide is removed, a dielectric layer(s) on a surface of the DTs is formed, a top plate material layer is deposited to fill the DTs, and the top plate material layer is removed beyond the DT to form a top plate.

公开(公告)号：US20210005760A1

公开(公告)日：2021-01-07

申请号：US17023639

申请日：2020-09-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Binghua Hu ,  Alexei Sadovnikov ,  Abbas Ali ,  Yanbiao Pan ,  Stefan Herzer

IPC: H01L29/94 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.

公开(公告)号：US10461072B2

公开(公告)日：2019-10-29

申请号：US15895694

申请日：2018-02-13

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Akram A. Salman ,  Binghua Hu

IPC: H01L21/762 ,  H01L27/02 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L21/763 ,  H01L21/8222 ,  H01L27/06

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

公开(公告)号：US20190207010A1

公开(公告)日：2019-07-04

申请号：US15859492

申请日：2017-12-30

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Michael Allen Ball ,  Jarvis Benjamin Jacobs ,  James Robert Todd

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/167 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/02 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L29/665 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/32137 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/4175 ,  H01L29/456

Abstract: An integrated circuit having silicide block integrated with CMOS transistors is formed by forming a silicide block layer of primarily silicon dioxide, free of silicon nitride and silicon oxy-nitride, at less than 400° C. prior to annealing the PMOS sources and drains. A spike anneal process concurrently anneals the PMOS sources and drains and densifies the silicide block layer. The NMOS drain junctions are less than 120 nanometers; the NMOS halo regions include boron. The NMOS and PMOS transistors are laterally separated by an STI oxide layer. A wet deglaze process prior to metal silicide formation removes less than 25 percent of the silicide block layer, and exposes sides of the NMOS drains less than 20 percent of the drain junction depth. The metal silicide does not extend down the NMOS drains sides, directly adjacent to the STI oxide layer, more than 20 percent of the drain junction depth.

公开(公告)号：US20190189751A1

公开(公告)日：2019-06-20

申请号：US16282374

申请日：2019-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Binghua Hu ,  Azghar H. Khazi-Syed ,  Shariq Arshad

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L21/225 ,  H01L21/266 ,  H01L21/265 ,  H01L21/306

CPC classification number: H01L29/1083 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/2253 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/66575

Abstract: A microelectronic device includes a substrate comprising a semiconductor material having a top surface. An epitaxial layer is located on the top surface of the substrate. A doped buried layer is located within the semiconductor material, and the top surface has a surface recess over the buried layer. The surface recess has a maximum step height no greater than about 5 nanometers. A method of forming the microelectronic device is also disclosed.

公开(公告)号：US20190157382A1

公开(公告)日：2019-05-23

申请号：US16241076

申请日：2019-01-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jun Cai ,  Binghua Hu

IPC: H01L29/06 ,  H01L21/761 ,  H01L29/866 ,  H01L29/66 ,  H01L29/868

CPC classification number: H01L29/0615 ,  H01L21/761 ,  H01L29/0626 ,  H01L29/66106 ,  H01L29/866 ,  H01L29/868

Abstract: In some embodiments, an apparatus comprises a semiconductor layer doped with a first-type dopant, a first region doped with the first-type dopant, a second region doped with the first-type dopant, and a third region doped with a second-type dopant, where the second-type dopant is opposite the first-type dopant. The first, second, and third regions are non-overlapping and are formed in the semiconductor layer. The third region is positioned between the first region and the second region. The apparatus also comprises a plurality of Zener implant regions buried in the semiconductor layer and the third region, where each of the plurality of Zener implant regions is configured to generate a different pinch-off region.

公开(公告)号：US20180076277A1

公开(公告)日：2018-03-15

申请号：US15264147

申请日：2016-09-13

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Hideaki Kawahara ,  Sameer P. Pendharkar

IPC: H01L49/02 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L29/08 ,  H01L21/306 ,  H01L29/06 ,  H01L27/06

CPC classification number: H01L28/40 ,  H01L21/0223 ,  H01L21/26513 ,  H01L21/30625 ,  H01L21/32055 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0847

Abstract: A deep trench capacitor and a method for providing the same in a semiconductor process are disclosed. The method includes forming a plurality of deep trenches in a first region of a semiconductor wafer, the first region having well doping of a first type. A dielectric layer is formed on a surface of the plurality of deep trenches and a doped polysilicon layer is deposited to fill the plurality of deep trenches, with the doped polysilicon being doped with a dopant of a second type. Shallow trench isolation is formed overlying the dielectric layer at an intersection of the dielectric layer with the surface of the semiconductor wafer.

公开(公告)号：US09741718B2

公开(公告)日：2017-08-22

申请号：US14803759

申请日：2015-07-20

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar ,  Seetharaman Sridhar ,  Jarvis Jacobs

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/40 ,  H01L29/08 ,  H01L29/417 ,  H01L21/761 ,  H01L29/78 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0883 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

公开(公告)号：US09583612B1

公开(公告)日：2017-02-28

申请号：US15003776

申请日：2016-01-21

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Binghua Hu ,  James Robert Todd

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/402 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/32 ,  H01L21/324 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0617 ,  H01L27/088 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/408 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7835

Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.

Abstract translation: 包括场致电FET的集成电路通过在氧化物掩模层中形成第一开口而形成，暴露漂移区域的区域。 在第一开口下将掺杂剂注入到基底中。 随后，沿着第一开口的横向边界形成电介质侧壁。 通过在由电介质侧壁暴露的第一开口的区域中的热氧化形成磁场消除氧化物。 注入的掺杂剂扩散到衬底中以形成漂移区域，横向延伸穿过氧化膜层。 在形成磁场释放氧化物层之后，去除电介质侧壁和氧化物掩模层。 栅极形成在场放电的FET的主体上并在相邻漂移区上方。 在与栅极相邻的磁场浮雕氧化物的正上方形成有场板。