公开(公告)号：US20140203388A1

公开(公告)日：2014-07-24

申请号：US14157891

申请日：2014-01-17

Applicant: Texas Instruments Incorporated

Inventor： James BECKER ,  Henry Litzmann EDWARDS

IPC: H01L31/0232 ,  H01L31/18

CPC classification number: H01L31/02327 ,  H01L31/02024 ,  H01L31/103

Abstract: An optical sensor includes a semiconductor substrate having a first conductive type. The optical sensor further includes a photodiode disposed on the semiconductor substrate and a metal layer. The photodiode includes a first semiconductor layer having the first conductive type and a second semiconductor layer, formed on the first semiconductor layer, including a plurality of cathodes having a second conductive type. The first semiconductor layer is configured to collect photocurrent upon reception of incident light. The cathodes are configured to be electrically connected to the first semiconductor layer and the second semiconductor layer is configured to, based on the collected photocurrent, to track the incident light. The metal layer further includes a pinhole configured to collimate the incident light, and the plurality of cathodes form a rotational symmetry of order n with respect to an axis of the pinhole

Abstract translation: 光学传感器包括具有第一导电类型的半导体衬底。 光学传感器还包括设置在半导体衬底上的光电二极管和金属层。 光电二极管包括具有第一导电类型的第一半导体层和形成在第一半导体层上的第二半导体层，其包括具有第二导电类型的多个阴极。 第一半导体层被配置为在接收到入射光时收集光电流。 阴极被配置为电连接到第一半导体层，并且第二半导体层被配置为基于收集的光电流来跟踪入射光。 金属层还包括被配置为准直入射光的针孔，并且多个阴极相对于针孔的轴线形成n阶的旋转对称

公开(公告)号：US20240230748A1

公开(公告)日：2024-07-11

申请号：US18442662

申请日：2024-02-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert Allan NEIDORFF ,  Henry Litzmann EDWARDS

IPC: G01R31/26 ,  G01R19/00 ,  G01R19/165 ,  G01R31/30 ,  G01R31/50

CPC classification number: G01R31/2621 ,  G01R19/0092 ,  G01R19/165 ,  G01R31/3008 ,  G01R31/50

Abstract: A system for determining the leakage current of a field effect transistor over temperature includes a metal oxide semiconductor field effect transistor (MOSFET) having first and second current terminals and a control terminal, wherein the first current terminal is coupled to a current measurement device. A switch is coupled to the control terminal and to a voltage source. The switch is configured to apply a voltage between a control terminal and a current terminal of the (MOSFET) responsive to a first signal, and apply approximately zero volts to the control terminal of the (MOSFET) responsive to a second signal.

公开(公告)号：US20230115019A1

公开(公告)日：2023-04-13

申请号：US18066511

申请日：2022-12-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Boguslaw KOCON ,  Henry Litzmann EDWARDS

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a switch element having a surface and first and second regions and including a first semiconductor material having a band-gap. The first region of the switch element is coupled to a source contact. A floating electrode has first and second ends. The first end of the floating electrode is coupled to the second region of the switch element. A voltage-support structure includes a second semiconductor material having a band-gap that is larger than the band-gap of the first semiconductor material. The voltage-support structure is in contact with the second end of the floating electrode. A drain contact is coupled to the voltage-support structure.

公开(公告)号：US20200066710A1

公开(公告)日：2020-02-27

申请号：US16666563

申请日：2019-10-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann EDWARDS ,  Akram A. SALMAN ,  Binghua HU

IPC: H01L27/02 ,  H01L21/265 ,  H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/763

Abstract: An integrated circuit (IC) includes a semiconductor substrate in which a plurality of spaced-apart deep trench (DT) structures are formed. The IC further includes a plurality of DEEPN diffusion regions, each DEEPN diffusion region surrounding a corresponding one of the DT structures. Each of the DEEPN diffusion regions merges with at least one neighboring DEEPN diffusion region that surrounds at least one neighboring DT structure. The merged DEEPN diffusion regions may partially isolate two electronic devices, e.g. ESD devices.

公开(公告)号：US20180151722A1

公开(公告)日：2018-05-31

申请号：US15865028

申请日：2018-01-08

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann EDWARDS ,  Binghua HU ,  James Robert TODD

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L29/10 ,  H01L21/265 ,  H01L29/08 ,  H01L29/06 ,  H01L21/324

CPC classification number: H01L29/7816 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate having a p-epi layer thereon, a p-body region in the p-epi layer and an ndrift (NDRIFT) region within the p-body to provide a drain extension region. A gate stack includes a gate dielectric layer over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region. A patterned gate electrode is on the gate dielectric. A DWELL region is within the p-body region. A source region is within the DWELL region, and a drain region is within the NDRIFT region. An effective channel length (Leff) for the LDMOS device is 75 nm to 150 nm which evidences a DWELL implant that utilized an edge of the gate electrode to delineate an edge of a DWELL ion implant so that the DWELL region is self-aligned to the gate electrode.

公开(公告)号：US20230101691A1

公开(公告)日：2023-03-30

申请号：US17489513

申请日：2021-09-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann EDWARDS

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

Abstract: A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.

公开(公告)号：US20210325443A1

公开(公告)日：2021-10-21

申请号：US17362706

申请日：2021-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert Allan NEIDORFF ,  Henry Litzmann EDWARDS

IPC: G01R31/26 ,  G01R31/30 ,  G01R19/00 ,  G01R19/165 ,  G01R31/50

Abstract: An example method provides a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method uses the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also uses the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further uses the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.

公开(公告)号：US20170033096A1

公开(公告)日：2017-02-02

申请号：US15292409

申请日：2016-10-13

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann EDWARDS ,  Akram A. SALMAN

IPC: H01L27/02 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/266 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L27/0262 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823892 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/66371 ,  H01L29/742

Abstract: An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.

Abstract translation: 集成电路包括NMOS SCR，其中NMOS晶体管的p型体阱为垂直NPN层堆叠提供基极层。 通过使用在基底区域上具有切口掩模元件的注入掩模注入p型掺杂剂来形成基底层，以便从基底区域阻挡p型掺杂剂。 基极层与集成电路中的逻辑元件中NMOS晶体管的p型体阱同时注入。 随后的退火导致p型掺杂剂扩散到基极区域中，形成具有较低掺杂密度的基极，即在NMOS SCR中的NMOS晶体管的主体阱的相邻区域。 NMOS SCR可以具有对称晶体管，漏极延伸晶体管，或者可以是具有与漏极延伸晶体管集成的对称晶体管的双向NMOS SCR。

公开(公告)号：US20250169193A1

公开(公告)日：2025-05-22

申请号：US19032752

申请日：2025-01-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann EDWARDS ,  Akram A. SALMAN ,  Binghua Hu

IPC: H10D89/60 ,  H01L21/265 ,  H01L21/762 ,  H01L21/763 ,  H10D62/10 ,  H10D62/17 ,  H10D84/01 ,  H10D84/03 ,  H10D84/40

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

公开(公告)号：US20230049751A1

公开(公告)日：2023-02-16

申请号：US17402287

申请日：2021-08-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rahmi HEZAR ,  Henry Litzmann EDWARDS ,  Miaad ALIROTEH ,  Srinath Mathur RAMASWAMY ,  Baher HAROUN ,  Gerd SCHUPPENER

IPC: H01L31/02 ,  H01L31/107 ,  G01S7/4861

Abstract: A sensor chip includes a sensor pixel. The sensor pixel includes an avalanche photodetector. A circuit is adjacent to the avalanche photodetector. The circuit is coupled to the avalanche photodetector. An isolation structure at least partially encloses the circuit and is between the avalanche photodetector and the circuit.