公开(公告)号：US20200279800A1

公开(公告)日：2020-09-03

申请号：US16878576

申请日：2020-05-19

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: In described examples, a terminal (e.g., a conductive terminal) includes a base material, a plating stack and a solder finish. The base material can be a metal, such as copper. The plating stack is arranged on a surface of the base material, and includes breaks in the plating stack. The breaks in the plating stack extend from a first surface of the plating stack to a second surface of the plating stack adjacent to the surface of the base material. The solder finish is coated over the breaks in the plating stack.

公开(公告)号：US20190109076A1

公开(公告)日：2019-04-11

申请号：US16151026

申请日：2018-10-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenivasan K. Koduri

IPC: H01L23/495

Abstract: In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The seminconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed.

公开(公告)号：US12074098B2

公开(公告)日：2024-08-27

申请号：US18308648

申请日：2023-04-27

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/49555 ,  H01L23/49805 ,  H01L24/48 ,  H01L24/49 ,  H05K3/3426 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/14

Abstract: A packaged electronic device includes a package structure with opposite first and second sides spaced apart from one another along a first direction, and opposite third and fourth sides spaced apart from one another along a second direction, as well as first and second leads. The first lead includes a first portion that extends outward from the third side of the package structure and extends downward toward a plane of the first side and away from a plane of the second side. The second lead includes a first portion that extends outward from the third side of the package structure, and the second lead extends upward toward the plane of the second side and away from the plane of the first side to allow connection to another circuit or component, such as a second packaged electronic device, a passive circuit component, a printed circuit board, etc.

公开(公告)号：US20240258211A1

公开(公告)日：2024-08-01

申请号：US18160226

申请日：2023-01-26

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri ,  Ryan Thorpe ,  Hank M. Sung

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H10N59/00

CPC classification number: H01L23/49558 ,  H01L21/4839 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49555 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H10N59/00 ,  H01L24/45 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/48151 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/85

Abstract: An example apparatus includes a metal leadframe that includes: first leads in a first portion; second leads in a second portion spaced from the first leads, the second leads isolated from the first leads; an isolation barrier mounted to a board side surface of the first portion of the metal leadframe; a semiconductor die mounted to the isolation barrier, the semiconductor die having a sensor on a device side surface facing the first portion of the leadframe, the semiconductor die cantilevered and having bond pads on the device side surface exposed in the opening in the metal leadframe; electrical connections coupling the bond pads and second leads in the second portion of the metal leadframe; and mold compound covering the semiconductor die, the electrical connections, the isolation barrier and portions of the first leads and the second leads, the mold compound forming a package body.

公开(公告)号：US11887906B2

公开(公告)日：2024-01-30

申请号：US17524562

申请日：2021-11-11

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  B81C1/00 ,  B81B3/00 ,  B81B7/00

CPC classification number: H01L23/3114 ,  B81B3/0083 ,  B81B7/0006 ,  B81B7/0067 ,  B81B7/0093 ,  B81C1/00095 ,  B81C1/00182 ,  B81C1/00317 ,  H01L23/481 ,  H01L24/09 ,  B81B2201/0264 ,  B81B2201/0292

Abstract: A die-wrapped packaged device includes at least one flexible substrate having a top side and a bottom side that has lead terminals, where the top side has outer positioned die bonding features coupled by traces to through-vias that couple through a thickness of the flexible substrate to the lead terminals. At least one die includes a substrate having a back side and a topside semiconductor surface including circuitry thereon having nodes coupled to bond pads. One of the sides of the die is mounted on the top side of the flexible circuit, and the flexible substrate has a sufficient length relative to the die so that the flexible substrate wraps to extend over at least two sidewalls of the die onto the top side of the flexible substrate so that the die bonding features contact the bond pads.

公开(公告)号：US11797732B2

公开(公告)日：2023-10-24

申请号：US17245000

申请日：2021-04-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ashish Khandelwal ,  Sreenivasan K. Koduri ,  Nikhil Gupta ,  Timothy W. Fischer

IPC: G06F30/27 ,  G06F30/392 ,  G06N3/084 ,  G06F30/398 ,  G06F30/337 ,  G06N20/00 ,  G06N3/08 ,  G06N20/20 ,  G06F30/367 ,  G06F30/373 ,  G06F30/3308 ,  G06F18/2415 ,  G06N3/045 ,  G06F111/20 ,  G06F111/04

CPC classification number: G06F30/27 ,  G06F18/24155 ,  G06F30/337 ,  G06F30/3308 ,  G06F30/367 ,  G06F30/373 ,  G06F30/392 ,  G06F30/398 ,  G06N3/045 ,  G06N3/08 ,  G06N3/084 ,  G06N20/00 ,  G06N20/20 ,  G06F2111/04 ,  G06F2111/20

Abstract: A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

公开(公告)号：US20230260879A1

公开(公告)日：2023-08-17

申请号：US18308648

申请日：2023-04-27

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H05K3/34

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/49805 ,  H01L23/49555 ,  H01L24/49 ,  H05K3/3426 ,  H01L24/48 ,  H01L2924/14 ,  H01L2224/48091 ,  H01L2224/48247

Abstract: A packaged electronic device includes a package structure with opposite first and second sides spaced apart from one another along a first direction, and opposite third and fourth sides spaced apart from one another along a second direction, as well as first and second leads. The first lead includes a first portion that extends outward from the third side of the package structure and extends downward toward a plane of the first side and away from a plane of the second side. The second lead includes a first portion that extends outward from the third side of the package structure, and the second lead extends upward toward the plane of the second side and away from the plane of the first side to allow connection to another circuit or component, such as a second packaged electronic device, a passive circuit component, a printed circuit board, etc.

公开(公告)号：US11727175B2

公开(公告)日：2023-08-15

申请号：US17245022

申请日：2021-04-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy W. Fischer ,  Ashish Khandelwal ,  Sreenivasan K. Koduri ,  Nikhil Gupta

IPC: G06F30/27 ,  G06F30/392 ,  G06N3/084 ,  G06F30/398 ,  G06F30/337 ,  G06N20/00 ,  G06N3/08 ,  G06N20/20 ,  G06F30/367 ,  G06F30/373 ,  G06F30/3308 ,  G06F18/2415 ,  G06N3/045 ,  G06F111/20 ,  G06F111/04

CPC classification number: G06F30/27 ,  G06F18/24155 ,  G06F30/337 ,  G06F30/3308 ,  G06F30/367 ,  G06F30/373 ,  G06F30/392 ,  G06F30/398 ,  G06N3/045 ,  G06N3/08 ,  G06N3/084 ,  G06N20/00 ,  G06N20/20 ,  G06F2111/04 ,  G06F2111/20

Abstract: A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

公开(公告)号：US20220277965A1

公开(公告)日：2022-09-01

申请号：US17746887

申请日：2022-05-17

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495

Abstract: A microelectronic device, in a multirow gull-wing chip scale package, has a die connected to intermediate pads by wire bonds. The intermediate pads are free of photolithographically-defined structures. An encapsulation material at least partially surrounds the die and the wire bonds, and contacts the intermediate pads. Inner gull-wing leads and outer gull-wing leads, located outside of the encapsulation material, are attached to the intermediate pads. The gull-wing leads have external attachment surfaces opposite from the intermediate pads. The external attachment surfaces of the outer gull-wing leads are located outside of the external attachment surfaces of the inner gull-wing leads. The microelectronic device is formed by mounting the die on a carrier, forming the intermediate pads without using a photolithographic process, and forming the wire bonds. The encapsulation material is formed, and the carrier is subsequently removed, exposing the intermediate pads. The gull-wing leads are formed on the intermediate pads.

公开(公告)号：US11264336B2

公开(公告)日：2022-03-01

申请号：US16680044

申请日：2019-11-11

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498

Abstract: In a described example, an apparatus includes a packaged device carrier having a board side surface and an opposing surface, the packaged device carrier having conductive leads having a first thickness spaced from one another; the conductive leads having a head portion attached to a dielectric portion, a middle portion extending from the head portion and extending away from the board side surface of the packaged device carrier at an angle to the opposing surface, and each lead having an end extending from the middle portion with a foot portion configured for mounting to a substrate.