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    Method of fabricating tunneling transistor
    13.
    发明授权
    Method of fabricating tunneling transistor 有权

    公开(公告)号：US10707305B2

    公开(公告)日：2020-07-07

    申请号：US16354126

    申请日：2019-03-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Cheng-Guo Chen ,  Kun-Yuan Wu ,  Tai-You Chen ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo

    IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/739 ,  H01L29/267

    Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

    SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
    16.
    发明申请
    SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20140361373A1

    公开(公告)日：2014-12-11

    申请号：US13913511

    申请日：2013-06-09

    Applicant: United Microelectronics Corp.

    Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Cheng-Guo Chen ,  Chien-Ting Lin

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7851 ,  H01L21/8234 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7855

    Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, wherein the first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

    Abstract translation: 半导体器件包括鳍结构，隔离结构，栅极结构和外延结构。 翅片结构从衬底的表面突出并且包括顶表面和两个侧壁。 隔离结构围绕翅片结构。 栅极结构覆盖鳍结构的一部分的顶表面和两个侧壁，并且覆盖隔离结构的一部分。 栅极结构下的隔离结构具有第一顶表面，并且栅极结构两侧的隔离结构具有第二顶表面，其中第一顶表面高于第二顶表面。 外延层设置在栅极结构的一侧并与鳍结构直接接触。

    Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures
    17.
    发明授权
    Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures 有权
    外延在PMOS和NMOS结构的源极和漏极区域中形成应力诱导外延层的工艺

    公开(公告)号：US08895396B1

    公开(公告)日：2014-11-25

    申请号：US13940220

    申请日：2013-07-11

    Applicant: United Microelectronics Corp.

    Inventor： Ssu-I Fu ,  Yu-Hsiang Hung ,  Cheng-Guo Chen ,  Chung-Fu Chang ,  Chien-Ting Lin

    IPC: H01L21/8236 ,  H01L21/8234

    CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    Abstract: An epitaxial process includes the following steps. A first gate and a second gate are formed on a substrate. Two first spacers are formed on the substrate beside the first gate and the second gate respectively. Two first epitaxial layers having first profiles are formed in the substrate beside the two first spacers respectively. A second spacer material is formed to cover the first gate and the second gate. The second spacer material covering the second gate is etched to form a second spacer on the substrate beside the second gate and expose the first epitaxial layer beside the second spacer while reserving the second spacer material covering the first gate. The exposed first epitaxial layer in the substrate beside the second spacer is replaced by a second epitaxial layer having a second profile different from the first profile.

    Abstract translation: 外延工艺包括以下步骤。 在基板上形成第一栅极和第二栅极。 分别在第一栅极和第二栅极旁边的基板上形成两个第一间隔物。 分别在两个第一间隔物旁边的衬底中形成具有第一轮廓的两个第一外延层。 形成第二间隔材料以覆盖第一栅极和第二栅极。 蚀刻覆盖第二栅极的第二间隔物材料，以在第二栅极旁边的衬底上形成第二间隔物，并在第二间隔物旁边露出第一外延层，同时保留覆盖第一栅极的第二间隔物材料。 在第二间隔物旁边的衬底中的暴露的第一外延层由具有不同于第一轮廓的第二轮廓的第二外延层代替。

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