公开(公告)号：US09431441B1

公开(公告)日：2016-08-30

申请号：US14834452

申请日：2015-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Chun-Yuan Wu ,  Chia-Fu Hsu

IPC: H01L29/10 ,  H01L27/146 ,  H01L29/786

CPC classification number: H01L27/14612 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L29/7869

Abstract: A back side illumination image sensor pixel structure includes a substrate having a front side and a back side opposite to the front side, a sensing device formed in the substrate to receive an incident light through the back side of the substrate, two oxide-semiconductor field effect transistor (OS FET) devices formed on the front side of the substrate, and a capacitor formed on the front side of the substrate. The two OS FET devices are directly stacked on the sensing device and the capacitor is directly stacked on the OS FET devices. The two OS FET devices overlap the sensing device, and the capacitor overlaps both of the OS FET devices and the sensing device.

Abstract translation: 背面照明图像传感器像素结构包括具有与前侧相反的前侧和后侧的基板，形成在基板中以接收穿过基板的背面的入射光的感测装置，两个氧化物半导体场 形成在基板的前侧的效应晶体管（OS FET）器件，以及形成在基板的前侧的电容器。 两个OS FET器件直接堆叠在感测器件上，电容器直接堆叠在OS FET器件上。 两个OS FET器件与感测器件重叠，并且电容器与OS FET器件和感测器件重叠。

公开(公告)号：US09412590B1

公开(公告)日：2016-08-09

申请号：US14840055

申请日：2015-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L21/321 ,  H01L21/4763 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L21/283

CPC classification number: H01L29/66477 ,  H01L21/02323 ,  H01L21/02554 ,  H01L21/02658 ,  H01L27/1207 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. A barrier layer is formed on a substrate. An annealing process is performed after the step of forming the barrier layer. A first oxygen treatment is performed on the barrier layer after the annealing process for forming a first oxygen provider layer on the barrier layer. An oxide semiconductor layer is then formed on the first oxygen provider layer.

Abstract translation: 氧化物半导体器件的制造方法包括以下步骤。 在基板上形成阻挡层。 在形成阻挡层的步骤之后进行退火处理。 在阻挡层上形成第一氧供体层的退火处理之后，在阻挡层上进行第一次氧处理。 然后在第一氧供体层上形成氧化物半导体层。

公开(公告)号：US20160104786A1

公开(公告)日：2016-04-14

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/092 ,  H01L21/28 ,  H01L21/321 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US20150069534A1

公开(公告)日：2015-03-12

申请号：US14023475

申请日：2013-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Cun Ke ,  Chih-Wei Yang ,  Kun-Yuan Lo ,  Chia-Fu Hsu ,  Shao-Wei Wang

IPC: H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在高k电介质层上形成第一底部阻挡金属（BBM）层; 进行热处理; 去除第一个BBM层; 以及在所述高k电介质层上形成第二BBM层。

公开(公告)号：US10109630B2

公开(公告)日：2018-10-23

申请号：US15604638

申请日：2017-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tian Choy Gan ,  Chu-Yun Hsiao ,  Chia-Fu Hsu

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/265

Abstract: The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.

公开(公告)号：US09780230B2

公开(公告)日：2017-10-03

申请号：US15368647

申请日：2016-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L29/45

CPC classification number: H01L29/7869 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696

Abstract: The present invention provides a semiconductor structure, including a base, a patterned oxide semiconductor (OS) layer, two source/drain regions, a protective layer, a gate layer and a gate dielectric layer. The patterned OS layer is disposed on the base. Two source/drain regions are disposed on the patterned OS layer and are separated by a recess. Each source/drain region includes an inner sidewall facing the recess and an outer sidewall opposite to the inner sidewall. The protective layer is disposed on a sidewall of the patterned OS layer but is not on the inner sidewall of the source/drain region. The gate layer is disposed on the patterned OS layer, and the gate dielectric layer is disposed between the gate layer and the patterned OS layer.

公开(公告)号：US20170222003A1

公开(公告)日：2017-08-03

申请号：US15493154

申请日：2017-04-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tian Choy Gan ,  Chu-Yun Hsiao ,  Chun-Che Huang ,  Chia-Fu Hsu

IPC: H01L29/423 ,  H01L23/535 ,  H01L21/02 ,  H01L29/06 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L29/4236 ,  H01L21/02274 ,  H01L21/76224 ,  H01L21/7684 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42384

Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

公开(公告)号：US09666471B2

公开(公告)日：2017-05-30

申请号：US14711777

申请日：2015-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tian Choy Gan ,  Chu-Yun Hsiao ,  Chun-Che Huang ,  Chia-Fu Hsu

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/762 ,  H01L21/768 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/4236 ,  H01L21/02274 ,  H01L21/76224 ,  H01L21/7684 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42384

Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

公开(公告)号：US09490265B2

公开(公告)日：2016-11-08

申请号：US14693886

申请日：2015-04-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu

IPC: H01L27/14 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/46 ,  H01L21/84 ,  H01L29/24

CPC classification number: H01L27/1207 ,  H01L21/02565 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/84 ,  H01L29/24 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66969 ,  H01L29/7869

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a metal-oxide semiconductor (MOS) transistor thereon, and an oxide semiconductor transistor adjacent to the MOS transistor. Preferably, the MOS transistor includes a first gate structure and a source/drain region adjacent to two sides of the gate structure, and the oxide semiconductor transistor includes a channel layer and the top surface of the channel layer is lower than the top surface of the first gate structure of the MOS transistor.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：其上具有金属氧化物半导体（MOS）晶体管的衬底和与MOS晶体管相邻的氧化物半导体晶体管。 优选地，MOS晶体管包括与栅极结构的两侧相邻的第一栅极结构和源极/漏极区，并且氧化物半导体晶体管包括沟道层，并且沟道层的顶表面低于栅极结构的顶表面 MOS晶体管的第一栅极结构。

公开(公告)号：US09385206B2

公开(公告)日：2016-07-05

申请号：US14919738

申请日：2015-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Mao Chiou ,  Shih-Chieh Hsu ,  Jian-Cun Ke ,  Chun-Lung Chen ,  Lung-En Kuo

IPC: H01L29/76 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/495 ,  H01L21/28088 ,  H01L21/31116 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the bottom of the spacer includes a tapered profile and the tapered profile comprises a convex curve.

Abstract translation: 公开了一种半导体器件。 半导体器件包括衬底，衬底上的栅极结构和与栅极结构相邻的间隔物，其中间隔物的底部包括锥形轮廓，并且锥形轮廓包括凸曲线。