公开(公告)号：US20150069534A1

公开(公告)日：2015-03-12

申请号：US14023475

申请日：2013-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Cun Ke ,  Chih-Wei Yang ,  Kun-Yuan Lo ,  Chia-Fu Hsu ,  Shao-Wei Wang

IPC: H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在高k电介质层上形成第一底部阻挡金属（BBM）层; 进行热处理; 去除第一个BBM层; 以及在所述高k电介质层上形成第二BBM层。

公开(公告)号：US20240234505A1

公开(公告)日：2024-07-11

申请号：US18105887

申请日：2023-02-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Kuang-Hsiu Chen ,  Shou-Hung Wu ,  Shao-Wei Wang ,  Yu-Ren Wang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a fin structure disposed on a substrate, and an epitaxial semiconductor layer disposed over an upper part of the fin structure and having an undercut. The epitaxial semiconductor layer has a right-left symmetric, concave polygonal cross-section.

公开(公告)号：US20230369460A1

公开(公告)日：2023-11-16

申请号：US17835977

申请日：2022-06-09

Applicant: United Microelectronics Corp.

Inventor： Kuang-Hsiu Chen ,  Wei-Chung Sun ,  Chao Nan Chen ,  Chun-Wei Yu ,  Kuan Hsuan Ku ,  Shao-Wei Wang

IPC: H01L29/66

CPC classification number: H01L29/66636 ,  H01L29/66575 ,  H01L29/66446 ,  H01L29/66795

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.

公开(公告)号：US09406772B1

公开(公告)日：2016-08-02

申请号：US14609446

申请日：2015-01-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shao-Wei Wang ,  Shu-Ming Yeh ,  Yu-Tung Hsiao

IPC: H01L29/76 ,  H01L29/51 ,  H01L29/423 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L29/513 ,  H01L21/28167 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor structure with a multilayer gate oxide is provided. The structure includes a substrate. A multilayer gate oxide is disposed on the substrate, wherein the multilayer gate oxide includes a first gate oxide and a second gate oxide. The first gate oxide contacts the substrate and the second gate oxide is disposed on and contacts the first gate oxide. The second gate oxide is hydrophilic. The first gate oxide is formed by a thermal oxidation process. The second gate oxide is formed by a chemical treatment.

Abstract translation: 提供具有多层栅极氧化物的半导体结构。 该结构包括基底。 多层栅极氧化物设置在基板上，其中多层栅极氧化物包括第一栅极氧化物和第二栅极氧化物。 第一栅极氧化物接触衬底，并且第二栅极氧化物设置在第一栅极氧化物上并与其接触。 第二栅极氧化物是亲水的。 第一栅极氧化物通过热氧化工艺形成。 第二栅极氧化物通过化学处理形成。

公开(公告)号：US20160133474A1

公开(公告)日：2016-05-12

申请号：US14537827

申请日：2014-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Feng Ku ,  Shao-Wei Wang ,  Yi-Hui Lin ,  Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L29/6656 ,  H01L21/28035

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底，其中栅极结构包括高k电介质层; 通过注入第一气体将栅极结构周围的环境压力增加到预定压力; 将环境压力降低到基础压力; 以及在所述栅极结构周围形成间隔物。

公开(公告)号：US09281374B2

公开(公告)日：2016-03-08

申请号：US14490679

申请日：2014-09-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsun-Min Cheng ,  Min-Chuan Tsai ,  Chih-Chien Liu ,  Jen-Chieh Lin ,  Pei-Ying Li ,  Shao-Wei Wang ,  Mon-Sen Lin ,  Ching-Ling Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/43 ,  H01L29/772 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4232 ,  H01L29/435 ,  H01L29/51 ,  H01L29/66045 ,  H01L29/66545 ,  H01L29/78

Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

Abstract translation: 位于基板上的金属栅极结构包括栅介质层，金属层和氮化铝钛金属层。 栅介质层位于衬底上。 金属层位于栅极电介质层上。 氮化铝钛金属层位于金属层上。

公开(公告)号：US11876122B2

公开(公告)日：2024-01-16

申请号：US17994375

申请日：2022-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wei Chang ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Fu-Jung Chuang ,  Shao-Wei Wang ,  Yu-Ren Wang ,  Chia-Yuan Chang

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/08 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/4983 ,  H01L21/0234 ,  H01L21/02332 ,  H01L21/02521 ,  H01L21/28123 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a semiconductor device. A substrate having a fin structure is provided. A dummy gate is formed on the fin structure. A polymer block is formed adjacent to a corner between the dummy gate and the fin structure. The polymer block is subjected to a nitrogen plasma treatment, thereby forming a nitridation layer in proximity to a sidewall of the dummy gate under the polymer block. After subjecting the polymer block to the nitrogen plasma treatment, a seal layer is formed on the sidewall of the dummy gate and on the polymer block. An epitaxial layer is then grown on a source/drain region of the fin structure. The dummy gate is then replaced with a metal gate.

公开(公告)号：US20230135072A1

公开(公告)日：2023-05-04

申请号：US18090510

申请日：2022-12-29

Applicant: United Microelectronics Corp.

Inventor： Hao Che Feng ,  Hung Jen Huang ,  Hsin Min Han ,  Shih-Wei Su ,  Ming Shu Chiu ,  Pi-Hung Chuang ,  Wei-Hao Huang ,  Shao-Wei Wang ,  Ping Wei Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311

Abstract: The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.

公开(公告)号：US09418853B1

公开(公告)日：2016-08-16

申请号：US14692736

申请日：2015-04-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shao-Wei Wang ,  Keng-Jen Lin ,  Yu-Tung Hsiao ,  Shu-Ming Yeh

IPC: H01L21/3205 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795

Abstract: The present invention provides a method for forming a stacked layer structure, including: first, a recess is provided, next, an oxide layer is formed in the recess, where the oxide layer has a thickness T1, a high-k layer is formed on the oxide layer, a barrier layer is formed on the high-k layer, a silicon layer is then formed on the barrier layer, afterwards, an annealing process is performed on the silicon layer, so as to form an oxygen-containing layer between the silicon layer and the barrier layer, where the oxide layer has a thickness T2 after the annealing process is performed, and satisfies the relationship: (T2−T1)/T1≦0.05, and the silicon layer and the oxygen-containing layer are removed.

Abstract translation: 本发明提供一种层叠结构体的形成方法，其特征在于，首先，设置凹部，在所述凹部形成有氧化层，其中氧化物层的厚度为T1，高k层形成在 氧化物层，在高k层上形成阻挡层，然后在阻挡层上形成硅层，然后在硅层上进行退火处理，以在其之间形成含氧层 硅层和阻挡层，其中氧化物层在退火处理之后具有厚度T2，并且满足关系：（T2-T1）/T1≤0.05，并且去除硅层和含氧层。

公开(公告)号：US20160172190A1

公开(公告)日：2016-06-16

申请号：US14571249

申请日：2014-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Lin Shih ,  Chueh-Yang Liu ,  Shao-Wei Wang ,  Che-Hung Huang ,  Po-Hua Jen ,  Shih-Hao Su

IPC: H01L21/02 ,  H01L21/283

CPC classification number: H01L21/28211 ,  H01L21/76224 ,  H01L21/823462

Abstract: A gate oxide formation process includes the following steps. A first gate oxide layer is formed on a substrate. The first gate oxide layer is thinned to a first predetermined thickness. The first gate oxide layer is then thickened to a second predetermined thickness, to thereby form a second gate oxide layer.

Abstract translation: 栅极氧化物形成工艺包括以下步骤。 在基板上形成第一栅氧化层。 第一栅极氧化物层被薄化到第一预定厚度。 然后将第一栅极氧化物层增厚至第二预定厚度，从而形成第二栅极氧化物层。