公开(公告)号：US11205609B2

公开(公告)日：2021-12-21

申请号：US16835349

申请日：2020-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Pin Hsu ,  Chih-Jung Wang ,  Chu-Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Purakh Raj Verma

IPC: H01L23/482 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/485

Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.

公开(公告)号：US20210384146A1

公开(公告)日：2021-12-09

申请号：US17408505

申请日：2021-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522

Abstract: An integrated circuit device includes a substrate; an integrated circuit region on the substrate, said integrated circuit region comprising a dielectric stack; a seal ring disposed in said dielectric stack and around a periphery of the integrated circuit region; a trench around the seal ring and exposing a sidewall of the dielectric stack; and a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

公开(公告)号：US20210375800A1

公开(公告)日：2021-12-02

申请号：US17402633

申请日：2021-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00

Abstract: A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

公开(公告)号：US11133270B1

公开(公告)日：2021-09-28

申请号：US16914482

申请日：2020-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/00 ,  H01L27/12 ,  H01L23/58 ,  H01L21/84 ,  H01L23/66 ,  H01L27/06

Abstract: An integrated circuit device includes a substrate, an integrated circuit region on the substrate, a seal ring disposed in a dielectric stack of the integrated circuit region and around a periphery of the integrated circuit region, a trench around the seal ring and exposing a sidewall of the dielectric stack, a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack; and a passivation layer over the moisture blocking layer.

公开(公告)号：US20130256765A1

公开(公告)日：2013-10-03

申请号：US13892324

申请日：2013-05-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chu-Chun Chang ,  Chun-Mao Chiou ,  Chiu-Te Lee

IPC: H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7843

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate; a first spacer disposed on a sidewall of the gate structure; a second spacer disposed around the first spacer, wherein the second spacer comprises a L-shaped cap layer and a cap layer on the L-shaped cap layer; a source/drain disposed in the substrate adjacent to two sides of the second spacer; and a CESL disposed on the substrate to cover the gate structure, wherein at least part of the second spacer and the CESL comprise same chemical composition and/or physical property.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 设置在所述基板上的栅极结构; 设置在所述栅极结构的侧壁上的第一间隔物; 设置在所述第一间隔件周围的第二间隔件，其中所述第二间隔件包括在所述L形盖层上的L形盖层和盖层; 设置在所述基板中的与所述第二间隔物的两侧相邻的源极/漏极; 以及设置在所述基板上以覆盖所述栅极结构的CESL，其中所述第二间隔物和所述CESL的至少一部分包含相同的化学组成和/或物理性质。

公开(公告)号：US12249545B2

公开(公告)日：2025-03-11

申请号：US17407157

申请日：2021-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/10 ,  H10B61/00 ,  H10B63/10 ,  H10N50/80 ,  H10N70/00

Abstract: An integrated circuit device includes a substrate; an integrated circuit area disposed on the substrate and comprising a dielectric stack; a seal ring disposed in the dielectric stack and around a periphery of the integrated circuit area; a cap layer on the dielectric stack; a trench around the seal ring and exposing a sidewall of the dielectric stack; a memory storage structure disposed on the cap layer; and a moisture blocking layer continuously covering the integrated circuit area and the memory storage structure. The moisture blocking layer extends to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

公开(公告)号：US12087712B2

公开(公告)日：2024-09-10

申请号：US18123317

申请日：2023-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/66 ,  H01L21/56 ,  H01L21/71 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58

CPC classification number: H01L23/66 ,  H01L21/56 ,  H01L21/71 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/564 ,  H01L23/585 ,  H01L24/05 ,  H01L2223/6661 ,  H01L2224/05624

Abstract: A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

公开(公告)号：US11894439B2

公开(公告)日：2024-02-06

申请号：US17068840

申请日：2020-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Heng-Ching Lin ,  Yu-Teng Tseng ,  Chu-Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L29/49 ,  H01L29/78 ,  H01L21/265 ,  H01L29/423

CPC classification number: H01L29/4983 ,  H01L29/4238 ,  H01L29/7835 ,  H01L21/26513

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a main branch extending along a first direction on the substrate and a sub-branch extending along a second direction adjacent to the main branch. The semiconductor device also includes a first doped region overlapping the main branch and the sub-branch according to a top view and a second doped region overlapping the first doped region.

公开(公告)号：US20210384093A1

公开(公告)日：2021-12-09

申请号：US17407157

申请日：2021-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/10 ,  H01L27/24 ,  H01L27/22 ,  H01L27/12 ,  H01L45/00 ,  H01L43/02

Abstract: An integrated circuit device includes a substrate; an integrated circuit area disposed on the substrate and comprising a dielectric stack; a seal ring disposed in the dielectric stack and around a periphery of the integrated circuit area; a cap layer on the dielectric stack; a trench around the seal ring and exposing a sidewall of the dielectric stack; a memory storage structure disposed on the cap layer; and a moisture blocking layer continuously covering the integrated circuit area and the memory storage structure. The moisture blocking layer extends to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

公开(公告)号：US20210375793A1

公开(公告)日：2021-12-02

申请号：US17401335

申请日：2021-08-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/00 ,  H01L21/84 ,  H01L23/58 ,  H01L23/66 ,  H01L27/12

Abstract: A method of forming integrated circuit device, including: providing a substrate; forming an integrated circuit region on the substrate, the integrated circuit region comprising a dielectric stack; forming a seal ring in the dielectric stack and around a periphery of the integrated circuit region; forming a trench around the seal ring and the trench exposing a sidewall of the dielectric stack; forming a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack; and forming a passivation layer over the moisture blocking layer.