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    TRANSISTOR STRUCTURE
    1.
    发明申请
    TRANSISTOR STRUCTURE 有权

    公开(公告)号：US20250048671A1

    公开(公告)日：2025-02-06

    申请号：US18459454

    申请日：2023-09-01

    Applicant: United Microelectronics Corp.

    Inventor： Hsuan-Kai Chen ,  Tun-Jen Cheng ,  Ching-Chung Yang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chiu-Te Lee

    IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423

    Abstract: A transistor structure including a substrate, a gate dielectric layer, a gate, a first doped region, a second doped region, a first drift region, and a dummy gate is provided. The gate dielectric layer is located on the substrate. The gate dielectric layer includes first and second portions. The second portion is connected to the first portion. The thickness of the second portion is greater than the thickness of the first portion. The gate is located on the first and second portions. The first doped region and the second doped region are located in the substrate on two sides of the gate dielectric layer. The first drift region is located in the substrate on one side of the gate. The second doped region is located in the first drift region. The dummy gate is located on the second portion between the gate and the second doped region.

    Transistor structure
    3.
    发明授权
    Transistor structure 有权

    公开(公告)号：US10431655B2

    公开(公告)日：2019-10-01

    申请号：US15924001

    申请日：2018-03-16

    Applicant: United Microelectronics Corp.

    Inventor： Yen-Ming Chen ,  Chiu-Ling Lee ,  Min-Hsuan Tsai ,  Chiu-Te Lee ,  Chih-Chung Wang

    IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08

    Abstract: A transistor structure including a substrate, a transistor device, a split buried layer, and a second buried layer is provided. The substrate has a device region. The transistor device is located in the device region. The split buried layer is located under the transistor device in the substrate and includes first buried layers separated from each other. The second buried layer is located under the split buried layer in the substrate and connects the first buried layers. The second buried layer and the split buried layer have a first conductive type. The transistor structure may have a higher breakdown voltage.

    Semiconductor structure and method for manufacturing the same
    4.
    发明授权
    Semiconductor structure and method for manufacturing the same 有权
    半导体结构及其制造方法

    公开(公告)号：US09224857B2

    公开(公告)日：2015-12-29

    申请号：US13674146

    申请日：2012-11-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Lin Chen ,  Chih-Chien Chang ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Chiu-Ling Lee

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08

    CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/66681

    Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug penetrating into the isolation and reaching the bottom thereof; and a first doping electrode region having the second conductive type, formed within the second well and below the isolation to connect the conductive plug.

    Abstract translation: 半导体结构包括具有第一导电类型的衬底; 具有形成在所述基板中并从所述基板的表面向下延伸的第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且从衬底的表面向下延伸，并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插塞穿透隔离并到达其底部; 以及具有第二导电类型的第一掺杂电极区域，形成在第二阱内并在隔离件下方以连接导电插塞。

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20130256765A1

    公开(公告)日：2013-10-03

    申请号：US13892324

    申请日：2013-05-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chu-Chun Chang ,  Chun-Mao Chiou ,  Chiu-Te Lee

    IPC: H01L29/78

    CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7843

    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate; a first spacer disposed on a sidewall of the gate structure; a second spacer disposed around the first spacer, wherein the second spacer comprises a L-shaped cap layer and a cap layer on the L-shaped cap layer; a source/drain disposed in the substrate adjacent to two sides of the second spacer; and a CESL disposed on the substrate to cover the gate structure, wherein at least part of the second spacer and the CESL comprise same chemical composition and/or physical property.

    Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 设置在所述基板上的栅极结构; 设置在所述栅极结构的侧壁上的第一间隔物; 设置在所述第一间隔件周围的第二间隔件，其中所述第二间隔件包括在所述L形盖层上的L形盖层和盖层; 设置在所述基板中的与所述第二间隔物的两侧相邻的源极/漏极; 以及设置在所述基板上以覆盖所述栅极结构的CESL，其中所述第二间隔物和所述CESL的至少一部分包含相同的化学组成和/或物理性质。

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