公开(公告)号：US09018087B2

公开(公告)日：2015-04-28

申请号：US14013429

申请日：2013-08-29

Applicant: United Microelectronics Corp.

Inventor： Hung-Lin Shih ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu

IPC: H01L21/00 ,  H01L21/28 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L21/02164 ,  H01L21/0217 ,  H01L21/30621 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.

Abstract translation: 提供一种制造半导体器件的方法，包括以下步骤。 在基板上形成虚拟栅极结构，其中虚拟栅极结构包括虚拟栅极和堆叠的硬掩模，并且堆叠的硬掩模从底部至顶部包括第一硬掩模层和第二硬掩模层。 在虚拟栅极结构的侧壁上形成间隔物。 在基板上形成掩模层。 在掩模层中形成与第二硬掩模层对应的开口。 去除第二个硬掩模层。 去除掩模层。 执行干蚀刻工艺以去除第一硬掩模层，其中干蚀刻工艺使用NF 3和H 2作为蚀刻剂。

公开(公告)号：US08962486B2

公开(公告)日：2015-02-24

申请号：US14142940

申请日：2013-12-30

Applicant: United Microelectronics Corp.

Inventor： Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Po-Chun Chen

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31144 ,  H01L21/76802

Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.

Abstract translation: 本发明提供一种在半导体衬底上形成开口的方法。 首先，提供基板。 然后在基板上形成介电层和盖层。 电介质层的厚度和盖层的厚度之比基本上在15和1.5之间。 接下来，在盖层上形成图案化的氮化硼层。 最后，通过使用图案化的硬掩模作为掩模来执行蚀刻工艺，以蚀刻覆盖层和电介质层，以在盖层和电介质层中形成开口。

公开(公告)号：US20140374909A1

公开(公告)日：2014-12-25

申请号：US14480648

申请日：2014-09-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Mao Hsu ,  Hsin-Fu Huang ,  Min-Chuan Tsai ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chin-Fu Lin ,  JING-GANG LI ,  Min-Hsien Chen ,  JIAN-HONG SU

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76846 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method.

Abstract translation: 公开了一种用金属层填充沟槽的方法。 提供具有多个支撑销的沉积装置。 设置有基板和介电层。 电介质层具有沟槽。 在将衬底放置在支撑销上以在沟槽中形成金属层之后立即执行第一沉积工艺，其中在第一沉积工艺期间，衬底的温度逐渐增加以达到预定温度。 当基板的温度达到预定温度时，执行第二沉积工艺以用金属层完全填充沟槽。 本发明还提供了具有大于1的反射率的铝层的半导体器件，其中通过使用该方法形成半导体器件。

公开(公告)号：US20140332824A1

公开(公告)日：2014-11-13

申请号：US14340267

申请日：2014-07-24

Applicant: United Microelectronics Corp.

Inventor： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Chih-Chien Liu

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/16 ,  H01L29/10 ,  H01L29/161

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/3141 ,  H01L21/3185 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/10879 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

Abstract: A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height.

Abstract translation: 描述用于形成FinFET的半导体结构。 半导体结构包括半导体衬底，衬底上的FinFET的多个奇数鳍片，以及FinFET的奇数鳍片之间的衬底上的FinFET的多个偶数鳍片。 FinFET的奇数鳍从衬底定义。 FinFET的均匀鳍片与宽度和材料中的至少一个中的FinFET的奇数鳍不同，并且可以与FinFET的高度的奇数鳍不同。

公开(公告)号：US08735269B1

公开(公告)日：2014-05-27

申请号：US13741402

申请日：2013-01-15

Applicant: United Microelectronics Corp.

Inventor： Chi-Yuan Sun ,  Chien-Hao Chen ,  Hsin-Fu Huang ,  Min-Chuan Tsai ,  Wei-Yu Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chin-Fu Lin

IPC: H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659

Abstract: The method for forming a semiconductor structure includes first providing a substrate. Then, a TiN layer is formed on the substrate at a rate between 0.3 and 0.8 angstrom/second. Finally, a poly-silicon layer is formed directly on the TiN layer. Since the TiN in the barrier layer is formed at a low rate so as to obtain a good quality, the defects in the TiN layer or the defects on the above layer, such as gate dummy layer or gate cap layer, can be avoided.

Abstract translation: 形成半导体结构的方法包括首先提供衬底。 然后，以0.3〜0.8埃的速度在基板上形成TiN层。 最后，直接在TiN层上形成多晶硅层。 由于阻挡层中的TiN以低的速率形成以获得良好的质量，因此可以避免TiN层中的缺陷或上层的缺陷，例如栅极虚设层或栅极盖层。

公开(公告)号：US11545521B2

公开(公告)日：2023-01-03

申请号：US17157952

申请日：2021-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Chen ,  Hui-Lin Wang ,  Yu-Ru Yang ,  Chin-Fu Lin ,  Yi-Syun Chou ,  Chun-Yao Yang

IPC: H01L27/22 ,  H01L23/552 ,  H01L43/10 ,  H01F41/34 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

公开(公告)号：US11450747B2

公开(公告)日：2022-09-20

申请号：US17218112

申请日：2021-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Hon-Huei Liu ,  Ming-Chang Lu ,  Chin-Fu Lin ,  Yu-Cheng Tung

IPC: H01L29/04 ,  H01L29/20 ,  H01L21/02 ,  H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L23/00 ,  H01L33/00 ,  H01L33/12 ,  H01L33/16 ,  H01L29/165

Abstract: The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.

公开(公告)号：US20210351347A1

公开(公告)日：2021-11-11

申请号：US17384817

申请日：2021-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Min Chou ,  Kuo-Chih Lai ,  Wei-Ming Hsiao ,  Hui-Ting Lin ,  Szu-Yao Yu ,  Nien-Ting Ho ,  Hsin-Fu Huang ,  Chin-Fu Lin

IPC: H01L45/00

Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

公开(公告)号：US20190267492A1

公开(公告)日：2019-08-29

申请号：US16413425

申请日：2019-05-15

Applicant: United Microelectronics Corp.

Inventor： Yen-Chen Chen ,  Xiao Wu ,  Hai Tao Liu ,  Ming Hua Du ,  Shouguo Zhang ,  Yao-Hung Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/24 ,  H01L29/45

Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.

公开(公告)号：US10141193B2

公开(公告)日：2018-11-27

申请号：US14949896

申请日：2015-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.