公开(公告)号：US20160018728A1

公开(公告)日：2016-01-21

申请号：US14335949

申请日：2014-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Teng-Chin Kuo ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G03F1/38 ,  H01L21/027 ,  G03F7/20

CPC classification number: G03F1/38 ,  G03F7/20 ,  H01L21/0274

Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.

Abstract translation: 本发明提供一种用于在半导体衬底上制造结构的光掩模，其包括光掩模衬底，第一图案，第二图案和禁止图案。 第一有源区，第二有源区被限定在光掩模基板上，除了第一有源区和第二有源区之外的区域被定义为禁止区。 第一图案设置在第一有源区中并对应于半导体衬底上的第一结构。 第二图案设置在第二有源区域中，并且对应于半导体衬底上的第二结构。 禁止图案设置在禁止区域中，其中禁止图案具有超过光刻分辨能力的尺寸，并且不用于在半导体基板上形成任何相应的结构。 本发明还提供一种制造半导体结构的方法。

公开(公告)号：US20150362905A1

公开(公告)日：2015-12-17

申请号：US14457136

申请日：2014-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chia-Chang Hsu ,  Teng-Chin Kuo ,  Chia-Hung Wang ,  Tuan-Yen Yu ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G05B19/18 ,  G03F7/20

CPC classification number: G03F7/70633 ,  G03F1/42 ,  G03F7/70491 ,  G05B19/188 ,  G05B2219/45027 ,  G05B2219/45031

Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Abstract translation: 校正重叠错误的方法包括以下步骤。 首先，捕获设置在基板上的覆盖标记，以生成重叠标记信息。 覆盖标记包括至少一对第一标记图案和至少第一标记图案上方的第二标记图案。 然后，计算叠加标记信息以产生两个第一标记图案之间的偏移值，并产生第二标记图案与第一标记图案之一之间的偏移值。 最后，偏移值用于补偿偏移值，以产生修正的移位值。

公开(公告)号：US09136140B2

公开(公告)日：2015-09-15

申请号：US14025524

申请日：2013-09-12

Applicant: United Microelectronics Corp.

Inventor： Wen-Liang Huang ,  Chia-Hung Lin ,  Chun-Chi Yu

IPC: H01L21/00 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/3088

Abstract: A patterning method is provided. First, a material layer is formed over a substrate. Thereafter, a plurality of directed self-assembly (DSA) patterns are formed on the material layer. Afterwards, a patterned photoresist layer is formed by using a single lithography process. The patterned photoresist layer covers a first portion of the DSA patterns and exposes a second portion of the DSA patterns. Further, the material layer is patterned by an etching process, using the patterned photoresist layer and the second portion of the DSA patterns as a mask.

Abstract translation: 提供了图案化方法。 首先，在基板上形成材料层。 此后，在材料层上形成多个定向自组装（DSA）图案。 之后，通过使用单个光刻工艺形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层覆盖DSA图案的第一部分并且暴露DSA图案的第二部分。 此外，通过蚀刻工艺，使用图案化的光致抗蚀剂层和DSA图案的第二部分作为掩模来对材料层进行图案化。

公开(公告)号：US20160103396A1

公开(公告)日：2016-04-14

申请号：US14512484

申请日：2014-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Teng-Chin Kuo ,  Chun-Chi Yu

IPC: G03F7/20

CPC classification number: G03F7/70058 ,  G03F7/70466 ,  G03F7/70625

Abstract: A double patterning method comprises the following steps. First of all, a target layer and a mask layer stacked thereon are provided. Next, a first pattern opening is formed in the mask layer, and a width of the first pattern opening is measured to obtain a measuring value. Then, a second pattern opening is formed in the mask layer based on the measuring value, wherein the second pattern opening and the first pattern opening are co-planar. Finally, a bias trimming process is performed to trim the first pattern opening and the second pattern opening.

Abstract translation: 双重图案化方法包括以下步骤。 首先，提供堆叠在其上的目标层和掩模层。 接下来，在掩模层中形成第一图案开口，并且测量第一图案开口的宽度以获得测量值。 然后，基于测量值在掩模层中形成第二图案开口，其中第二图案开口和第一图案开口是共面的。 最后，执行偏置修剪处理以修剪第一图案开口和第二图案开口。

公开(公告)号：US20150293461A1

公开(公告)日：2015-10-15

申请号：US14279039

申请日：2014-05-15

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Chia-Chang Hsu ,  Yi-Ting Chen ,  Teng-Chin Kuo ,  Chun-Chi Yu

IPC: G03F7/20

CPC classification number: G03F7/70516

Abstract: An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset a1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset a1 therebetween. The second overlap mark includes at least two sets of X-directional linear patterns, having a preset offset b1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset b1 therebetween. The preset offsets a1 and b1 are not equal.

Abstract translation: 提供重叠标记集以具有两个位于相同图案层的至少第一和第二重叠标记。 第一重叠标记包括至少两组X方向线性图案，其间具有预置偏移量a1; 以及至少两组Y方向线性图案，其间具有预设偏移量a1。 第二重叠标记包括至少两组X方向线性图案，其间具有预设偏移量b1; 以及至少两组Y方向线性图案，其间具有预设偏移量b1。 预置偏移量a1和b1不相等。

公开(公告)号：US09147601B2

公开(公告)日：2015-09-29

申请号：US14541148

申请日：2014-11-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Chun-Chi Yu

IPC: H01L21/311 ,  H01L21/302 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/027

CPC classification number: H01L21/76816 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139

Abstract: The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned layer is formed on the blocking layer such that a sidewall of the blocking layer is completely covered by the patterned layer. The patterned layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.

Abstract translation: 本发明提供一种形成通孔的方法。 首先，提供基板。 在基板上限定多个第一区域。 在基板上形成介电层和阻挡层。 在阻挡层上形成图案层，使得阻挡层的侧壁被图案化层完全覆盖。 图案化层包括以规则阵列布置的多个孔，其中孔阵列的面积大于第一区域的面积。 通过使用图案化层作为掩模来去除第一区域中的阻挡层。 最后，电介质层被图案化以在第一区域中的电介质层中至少形成通孔。

公开(公告)号：US09007571B2

公开(公告)日：2015-04-14

申请号：US13971776

申请日：2013-08-20

Applicant: United Microelectronics Corp.

Inventor： Wei-Jhe Tzai ,  Kuei-Chun Hung ,  Chun-Chi Yu ,  Chien-Hao Chen ,  Chia-Ching Lin

IPC: G01N21/00 ,  G03F9/00

CPC classification number: G03F7/70633

Abstract: A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark.

Abstract translation: 提供重叠标记的测量方法。 用光学测量工具的多个不同波长区域测量晶片上的覆盖标记，以便获得对应于波长区域的多个覆盖值。 用电测量工具测量晶片上的覆盖标记以获得参考覆盖值。 对应于最接近参考叠加值的覆盖值的波长区域被确定为覆盖标记的正确波长区域。

公开(公告)号：US20150072529A1

公开(公告)日：2015-03-12

申请号：US14541148

申请日：2014-11-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Chun-Chi Yu

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/76816 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139

Abstract: The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned layer is formed on the blocking layer such that a sidewall of the blocking layer is completely covered by the patterned layer. The patterned layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.

Abstract translation: 本发明提供一种形成通孔的方法。 首先，提供基板。 在基板上限定多个第一区域。 在基板上形成介电层和阻挡层。 在阻挡层上形成图案层，使得阻挡层的侧壁被图案化层完全覆盖。 图案化层包括以规则阵列布置的多个孔，其中孔阵列的面积大于第一区域的面积。 通过使用图案化层作为掩模来去除第一区域中的阻挡层。 最后，电介质层被图案化以在第一区域中的电介质层中至少形成通孔。

公开(公告)号：US20150055125A1

公开(公告)日：2015-02-26

申请号：US13971776

申请日：2013-08-20

Applicant: United Microelectronics Corp.

Inventor： Wei-Jhe Tzai ,  Kuei-Chun Hung ,  Chun-Chi Yu ,  Chien-Hao Chen ,  Chia-Ching Lin

IPC: G03F9/00

CPC classification number: G03F7/70633

Abstract: A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark.

Abstract translation: 提供重叠标记的测量方法。 用光学测量工具的多个不同波长区域测量晶片上的覆盖标记，以便获得对应于波长区域的多个覆盖值。 用电测量工具测量晶片上的覆盖标记以获得参考覆盖值。 对应于最接近参考叠加值的覆盖值的波长区域被确定为覆盖标记的正确波长区域。

公开(公告)号：US11043460B2

公开(公告)日：2021-06-22

申请号：US17000365

申请日：2020-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Wei Cheng ,  Bo-Jou Lu ,  Chun-Chi Yu

IPC: H01L23/544 ,  H01L21/66

Abstract: An overlay mark structure includes a plurality of first patterns of a previous layer and a plurality of second patterns of a current layer. Each of the second patterns includes a first section and a second section. The first section is disposed corresponding to one of the first patterns in a vertical direction. The first section partially overlaps the first pattern corresponding to the first section in the vertical direction. The second section is separated from the first section in an elongation direction of the second pattern. A part of the first pattern corresponding to the first section is disposed between the first section and the second section in the elongation direction of the second pattern. A measurement method of the overlay mark structure includes performing a diffraction-based overlay measurement between each of the first sections and the first pattern overlapping the first section.