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    Method for correcting critical dimension measurements of lithographic tool
    1.
    发明授权
    Method for correcting critical dimension measurements of lithographic tool 有权

    公开(公告)号：US12147163B2

    公开(公告)日：2024-11-19

    申请号：US17528295

    申请日：2021-11-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Yu Hsieh ,  Kuan-Ying LAi ,  Chang-Mao Wang ,  Chien-Hao Chen ,  Chun-Chi Yu

    IPC: G03F7/00

    Abstract: A method for correcting critical dimension (CD) measurements of a lithographic tool includes steps as follows. A correction pattern having a first sub-pattern parallel to a first direction and a second sub-pattern parallel to a second direction is provided on a lithographic mask; wherein the first sub-pattern and the second sub-pattern come cross with each other. A first After-Develop-Inspection critical dimension (ADI CD) of a developed pattern formed on a photo-sensitive layer and transferred from the correction pattern is measured using the lithographic tool along a first scanning direction. A second ADI CD of the developed pattern is measured using the lithographic tool along a second scanning direction. The first ADI CD is subtracted from the second ADI CD to obtain a measurement bias value. Exposure conditions and/or measuring parameters of the lithographic tool are adjusted according to the measurement bias value.

    Overlap mark set and method for selecting recipe of measuring overlap error
    5.
    发明授权
    Overlap mark set and method for selecting recipe of measuring overlap error 有权
    重叠标记集和选择测量重叠误差的方法

    公开(公告)号：US09482964B2

    公开(公告)日：2016-11-01

    申请号：US14279039

    申请日：2014-05-15

    Applicant: United Microelectronics Corp.

    Inventor： En-Chiuan Liou ,  Chia-Chang Hsu ,  Yi-Ting Chen ,  Teng-Chin Kuo ,  Chun-Chi Yu

    IPC: G03F7/20

    CPC classification number: G03F7/70516

    Abstract: An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset a1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset a1 therebetween. The second overlap mark includes at least two sets of X-directional linear patterns, having a preset offset b1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset b1 therebetween. The preset offsets a1 and b1 are not equal.

    Abstract translation: 提供重叠标记集以具有两个位于相同图案层的至少第一和第二重叠标记。 第一重叠标记包括至少两组X方向线性图案，其间具有预置偏移量a1; 以及至少两组Y方向线性图案，其间具有预设偏移量a1。 第二重叠标记包括至少两组X方向线性图案，其间具有预设偏移量b1; 以及至少两组Y方向线性图案，其间具有预设的偏移量b1。 预置偏移量a1和b1不相等。

    PATTERNING METHOD AND OVERLAY MESUREMENT METHOD
    6.
    发明申请
    PATTERNING METHOD AND OVERLAY MESUREMENT METHOD 有权

    公开(公告)号：US20220392768A1

    公开(公告)日：2022-12-08

    申请号：US17341183

    申请日：2021-06-07

    Applicant: United Microelectronics Corp.

    Inventor： Yi Jing Wang ,  Chia-Chang Hsu ,  Chien-Hao Chen ,  Chang-Mao Wang ,  Chun-Chi Yu

    IPC: H01L21/033 ,  H01L21/311 ,  H01L23/544 ,  H01L21/66 ,  G03F7/20

    Abstract: The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

    Photo-mask and method of manufacturing semiconductor structures by using the same
    8.
    发明授权
    Photo-mask and method of manufacturing semiconductor structures by using the same 有权
    光掩模及其制造方法

    公开(公告)号：US09448471B2

    公开(公告)日：2016-09-20

    申请号：US14335949

    申请日：2014-07-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Teng-Chin Kuo ,  Yuan-Chi Pai ,  Chun-Chi Yu

    IPC: G03F1/38 ,  G03F7/20 ,  H01L21/027

    CPC classification number: G03F1/38 ,  G03F7/20 ,  H01L21/0274

    Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.

    Abstract translation: 本发明提供一种用于在半导体衬底上制造结构的光掩模，其包括光掩模衬底，第一图案，第二图案和禁止图案。 第一有源区，第二有源区被限定在光掩模基板上，除了第一有源区和第二有源区之外的区域被定义为禁止区。 第一图案设置在第一有源区中并对应于半导体衬底上的第一结构。 第二图案设置在第二有源区域中，并且对应于半导体衬底上的第二结构。 禁止图案设置在禁止区域中，其中禁止图案具有超过光刻分辨能力的尺寸，并且不用于在半导体基板上形成任何相应的结构。 本发明还提供一种制造半导体结构的方法。

    Method of forming a photoresist pattern
    9.
    发明申请
    Method of forming a photoresist pattern 审中-公开
    形成光致抗蚀剂图案的方法

    公开(公告)号：US20140120476A1

    公开(公告)日：2014-05-01

    申请号：US13661050

    申请日：2012-10-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tuan-Yen Yu ,  Yuan-Chi Pai ,  Chun-Chi Yu

    IPC: G03F7/20

    CPC classification number: G03F7/2041 ,  G03F7/11 ,  G03F7/38 ,  G03F7/40

    Abstract: A method of forming a photoresist pattern, in which, a substrate is coated with a photoresist layer, an exposure process is performed on the photoresist layer to expose the photoresist layer, the photoresist layer is rinsed with a surfactant after the exposure process is performed, and the photoresist layer is post-exposure baked after the photoresist layer is rinsed with the surfactant.

    Abstract translation: 在光致抗蚀剂层上进行形成光致抗蚀剂图案的方法，其中基板涂覆有光致抗蚀剂层，曝光处理以曝光光致抗蚀剂层，在曝光处理之后用表面活性剂冲洗光致抗蚀剂层， 在用表面活性剂冲洗光致抗蚀剂层之后，对光致抗蚀剂层进行后曝光烘烤。

    Method of removing step height on gate structure
    10.
    发明授权
    Method of removing step height on gate structure 有权

    公开(公告)号：US12211699B2

    公开(公告)日：2025-01-28

    申请号：US17857158

    申请日：2022-07-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yeh-Sheng Lin ,  Chang-Mao Wang ,  Chun-Chi Yu ,  Chung-Yi Chiu

    IPC: H01L21/311 ,  H01L21/768

    Abstract: A method of removing a step height on a gate structure includes providing a substrate. A gate structure is disposed on the substrate. A dielectric layer covers the gate structure and the substrate. Then, a composite material layer is formed to cover the dielectric layer. Later, part of the composite material layer is removed to form a step height disposed directly on the gate structure. Subsequently, a wet etching is performed to remove the step height. After the step height is removed, the dielectric layer is etched to form a first contact hole to expose the gate structure.

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