公开(公告)号：GB2451526B

公开(公告)日：2012-04-25

申请号：GB0716920

申请日：2007-08-30

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL

IPC: H03F1/02 ,  H02M3/07

Abstract: An amplifier circuit comprises an input, for receiving an input signal to be amplified; a preamplifier, for amplifying the input signal based on a variable gain; a power amplifier for amplifying the signal output from the preamplifier; and a variable voltage power supply for supplying one or more supply voltages to the power amplifier. The supply voltages are adjusted based on the variable gain or the input digital signal. According to other aspects of the invention, a power supply of an amplifier circuit is clocked using a clock signal, whereby the clock signal has a frequency that varies in accordance with a volume signal or an input signal.

公开(公告)号：GB2484010A

公开(公告)日：2012-03-28

申请号：GB201116744

申请日：2006-08-31

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL ,  PENNOCK JOHN LAURENCE

IPC: H02M3/155

Abstract: A DC-DC converter circuit comprising a switch network for converting a voltage input terminal, inductor terminal and first and second output terminal wherein the switch network is arranged such that four switches of the network can be operated in use to generate a positive output voltage at the first output terminal and a negative output voltage at the second output terminal. The invention is of particular use in an audio amplifier.

公开(公告)号：GB2478457B

公开(公告)日：2011-12-07

申请号：GB201108796

申请日：2006-12-22

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL

IPC: H02M3/07

Abstract: A charge pump circuit, and associated method and apparatuses, for providing a split-rail voltage supply, the circuit having a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of said states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage and centered on the voltage at the common terminal.

公开(公告)号：GB2475636B

公开(公告)日：2011-09-07

申请号：GB201103080

申请日：2006-12-22

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL ,  PENNOCK JOHN LAURENCE ,  FRITH PETER JOHN

IPC: H03F1/02 ,  H02M3/07 ,  H03G1/00

公开(公告)号：GB2459108A

公开(公告)日：2009-10-14

申请号：GB0806447

申请日：2008-04-09

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL

IPC: H03L7/18

Abstract: A phase / frequency locked loop (PLL / FLL) circuit is provided for generating a clock signal for a DC-DC power converter. Within the locked loop circuit (200), a dither signal is generated (230) and used to add (235) a dither component to the control voltage on the loop integrating / filter capacitor (250). It is stated that the dither value is non zero at all times. In the frequency domain, the spectrum of the dithered clock signal so produced (fig.5) is spread out in contrast with that of an un-dithered signal (fig.2), with beneficial reduction of electromagnetic interference.

公开(公告)号：GB2456004A

公开(公告)日：2009-07-01

申请号：GB0725342

申请日：2007-12-28

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL

IPC: H03L7/081

Abstract: A frequency synthesiser comprises an oscillator 43, for example a numerically controller oscillator, for generating a first signal. An edge combiner 45 is provided for generating a second signal derived from the first signal, for example using two or more tap signals from the oscillator, the second signal having a frequency that is greater than that of the first signal. A detector 33 receives an input reference signal Fin and a feedback signal 35, and generates an output signal 37 that is used to provide an input to the oscillator, such that the oscillator operates in a locked loop mode of operation. The feedback signal to the detector is taken from the output of the edge combiner 45 rather than directly from the output of the oscillator, thus compensating for errors introduced by the edge combiner 45. The feedback signal may also pass through a divider 36. The frequency synthesiser may also include a sigma-delta modulator (47, fig.4) which is clocked by either the first signal or the second signal depending on power requirements. Keywords: synthesizer, synthesizer, edge combiner, frequency multiple.

公开(公告)号：GB2451526A

公开(公告)日：2009-02-04

申请号：GB0716920

申请日：2007-08-30

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL

IPC: H03F1/02 ,  H02M3/07

Abstract: Smaller FET switches are selected in a switching converter 604 when a low output current is required. This reduces the gate capacitance to be charged and discharged in each switching cycle and so improves converter efficiency. Larger FETs are used when a higher output current is required, to reduce conduction losses. The converter provides tracking power supplies for an audio amplifier 106. The FET gate width may be selected by unit 606 in dependence on the envelope of the input audio signal. Alternatively, the gate width may be selected in dependence on a volume control signal (figure 10). Switch size may be adapted in dependence on both volume and input envelope. The switching converter may be a charge pump (figures 14,15).

公开(公告)号：GB2519540A

公开(公告)日：2015-04-29

申请号：GB201318745

申请日：2013-10-23

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL ,  IDO TORU

IPC: H03F3/217

Abstract: Switching losses in a class-D audio amplifier are reduced by decreasing the switching frequency at low input signal amplitudes. The required minimum of the ratio of the switching frequency to the signal frequency for stable operation has been found to be lower at low signal amplitudes. The amplitude of the ramp or sawtooth waveform generated by circuit 302 is maintained invariant with frequency by altering the magnitude of the switched currents (figure 6) and/or integrating capacitors (figure 10) with respect to the selected switching frequency. Output signal transients caused by the frequency change may be reduced by using gradual and smooth frequency transitions (figure 9) and by changing frequency only at the peaks of the sawtooth waveform (figure 7). Where only discrete frequencies are available a sigma-delta modulator (1101, figure 11) may transition repeatedly between the frequencies to approximate the required smooth frequency transition. The loop filter bandwidth may be programmable (figure 14) and may be decreased during silence or low signal levels, which permits yet lower switching frequencies. The sawtooth waveform generator may be merged with the loop filter (figure 15).

公开(公告)号：GB2515526A

公开(公告)日：2014-12-31

申请号：GB201311375

申请日：2013-06-26

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL

IPC: H03M3/04 ,  G10L25/78

Abstract: An analogue-to-digital converter for speech signals is operable in a low-power input monitoring mode to save standby power and is then put into a high-resolution mode when input signals are detected so that speech recognition may be performed by a succeeding DSP (figure 9). The signal detector 252 selects the high-resolution mode by enabling the feedback DAC 274 and loop filter 276, and by selecting the filter output Sfilt instead of the signal input Sin. The quantiser 278, which may comprise a voltage-controlled oscillator feeding a counter (300,302, figure 11), may also be placed in a high-resolution mode (figures 13 and 14). To further reduce power consumption the DSP is enabled only when input signals are detected, with full speech recognition operation of the DSP being enabled only when a trigger phase has been detected (figure 4).

公开(公告)号：GB2486698B

公开(公告)日：2014-01-15

申请号：GB201021801

申请日：2010-12-23

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL ,  PENNOCK JOHN LAURENCE ,  FRITH PETER JOHN

IPC: H02M3/07

Abstract: A bipolar output charge pump circuit 100 is provided having a network of switching paths 110 for selectively connecting an input node (VV) and a reference node (VG) for connection to an input voltage, a first pair of output nodes (VP, VN), two pairs of flying capacitor nodes (CF1A, CF1B; CF2A, CF2B), and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors (CF1, CF2) connected to the two pairs of flying capacitor nodes, to provide a first mode and a second mode when in use with two flying capacitors connected to the flying capacitor nodes, wherein at least the first mode corresponds to a bipolar output voltage of +/-3VV, +/-VV/5 or +/-VV/6.