-
公开(公告)号：WO2012080742A3
公开(公告)日：2012-08-02
申请号：PCT/GB2011052492
申请日：2011-12-16
Applicant: WOLFSON MICROELECTRONICS PLC , LESSO JOHN PAUL
Inventor： LESSO JOHN PAUL
IPC: H03F1/30
CPC classification number: H03F3/181 , H03F1/304 , H03F3/183 , H03F2200/03 , H03K3/013
Abstract: This application describes apparatus and method for DC offset compensation. An amplifier (102) receives an input signal (AIN) and provides an amplified output signal (SOUT) and a feedback path provides DC offset compensation. The feedback path comprises at least one voltage controlled oscillator (VCO) (108) and a counter (109). The VCO provides, over time, a first VCO output signal based on said amplified output signal and a second VCO output signal based on a reference signal (VREF). The counter generates first pulse counts based upon the first VCO output signal and second pulse counts based upon the second VCO output signal and provides a compensation signal based on a comparison of the first and second pulse counts. One voltage controlled oscillator (108) may sequentially receive a signal based on said amplifier output signal and the reference signal from a multiplexer (110) so as to sequentially produce the first and second VCO output signals.
Abstract translation: 本申请描述了用于DC偏移补偿的装置和方法。 放大器（102）接收输入信号（AIN）并提供放大的输出信号（SOUT），并且反馈路径提供DC偏移补偿。 反馈路径包括至少一个压控振荡器（VCO）（108）和计数器（109）。 VCO随时间提供基于所述放大的输出信号的第一VCO输出信号和基于参考信号（VREF）的第二VCO输出信号。 计数器基于第一VCO输出信号和基于第二VCO输出信号的第二脉冲计数产生第一脉冲计数，并且基于第一和第二脉冲计数的比较来提供补偿信号。 一个压控振荡器（108）可以基于所述放大器输出信号和来自多路复用器（110）的参考信号来顺序地接收信号，以便顺序地产生第一和第二VCO输出信号。
-
公开(公告)号：WO2012085598A3
公开(公告)日：2012-11-15
申请号：PCT/GB2011052580
申请日：2011-12-23
Applicant: WOLFSON MICROELECTRONICS PLC , LESSO JOHN PAUL , FRITH PETER JOHN , PENNOCK JOHN LAURENCE
Inventor： LESSO JOHN PAUL , FRITH PETER JOHN , PENNOCK JOHN LAURENCE
CPC classification number: H02M3/07 , H02M1/00 , H02M2001/0083 , H02M2001/009 , H03F3/181
Abstract: A bipolar output charge pump circuit 100 is provided having a network of switching paths 110 for selectively connecting an input node (VV) and a reference node (VG) for connection to an input voltage, a first pair of output nodes (VP, VN) and a second pair of output nodes (VQ, VM), and two pairs of flying capacitor nodes (CF1A, CF1B; CF2A, CF2B), and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors (CF1, CF2) connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes (VP, VN) and a second bipolar output voltage at the second pair of bipolar output nodes (VQ, VM).
Abstract translation: 提供双极性输出电荷泵电路100，其具有用于选择性地连接用于连接到输入电压的输入节点（VV）和参考节点（VG）的开关路径110的网络，第一对输出节点（VP，VN） 以及第二对输出节点（VQ，VM）和两对飞行电容器节点（CF1A，CF1B; CF2A，CF2B）和用于控制交换路径网络的切换的控制器。 控制器可操作以在与两对飞跨电容器节点连接的两个飞行电容器（CF1，CF2）使用时控制开关路径网络，以在第一对输出节点（VP， VN）和在第二对双极输出节点（VQ，VM）处的第二双极性输出电压。
-
公开(公告)号：WO2013076470A3
公开(公告)日：2013-07-25
申请号：PCT/GB2012052868
申请日：2012-11-20
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： LESSO JOHN PAUL
CPC classification number: H03L7/0994 , H03L7/235
Abstract: A clock generator receives a first input clock signal and a second input clock signal. A first frequency comparator generates a first frequency comparison signal based on a ratio of a frequency of the output clock signal to a frequency of the first input clock signal, and a first subtractor forms a first error signal representing a difference between an input desired frequency ratio and the first frequency comparison signal. A first digital filter receives the first error signal and forms a filtered first error signal. A second frequency comparator generates a second frequency comparison signal based on a ratio of a frequency of the output clock signal to a frequency of the second input clock signal, and a second subtractor forms a second error signal representing a difference between the filtered first error signal and the second frequency comparison signal. A second digital filter receives the second error signal and forms a filtered second error signal. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.
Abstract translation: 时钟发生器接收第一输入时钟信号和第二输入时钟信号。 第一频率比较器基于输出时钟信号的频率与第一输入时钟信号的频率的比率产生第一频率比较信号，第一减法器形成第一误差信号，其表示输入的期望频率比 和第一频率比较信号。 第一数字滤波器接收第一误差信号并形成滤波后的第一误差信号。 第二频率比较器基于输出时钟信号的频率与第二输入时钟信号的频率的比率产生第二频率比较信号，第二减法器形成表示滤波后的第一误差信号之间的差的第二误差信号 和第二频率比较信号。 第二数字滤波器接收第二误差信号并形成滤波后的第二误差信号。 数字振荡器接收经滤波的第二误差信号并产生输出时钟信号。 结果，输出时钟信号在抖动频率的有用范围和第二输入时钟信号的频率精度上具有第一输入时钟信号的抖动特性。
-
公开(公告)号：WO2009136198A3
公开(公告)日：2010-07-15
申请号：PCT/GB2009050476
申请日：2009-05-07
Applicant: WOLFSON MICROELECTRONICS PLC , STEELE COLIN FINDLAY , STOJANOVIC GORAN , LESSO JOHN PAUL
Inventor： STEELE COLIN FINDLAY , STOJANOVIC GORAN , LESSO JOHN PAUL
CPC classification number: G01D5/24 , G01D3/032 , H04R3/00 , H04R19/005 , H04R19/04
Abstract: A capacitive transducer circuit comprises a capacitive transducer having first and second electrodes. The first and second electrodes are biased by respective first and second bias voltages. An amplifier is connected to receive a first analogue signal on an input terminal, the first analogue signal being generated by the capacitive transducer, and to generate a second analogue signal on an output terminal. A digital feedback circuit is connected between the output terminal of the amplifier and the input terminal of the amplifier. The digital feedback circuit is configured to provide one of said first or second bias voltages. The output of a voltage source which provides the other bias voltage for the capacitive transducer may be filtered by a low pass filter. The low pass filter may comprise a switched capacitor filter circuit.
Abstract translation: 电容式换能器电路包括具有第一和第二电极的电容换能器。 第一和第二电极被相应的第一和第二偏置电压偏置。 放大器被连接以在输入端子上接收第一模拟信号，第一模拟信号由电容换能器产生，并在输出端产生第二模拟信号。 数字反馈电路连接在放大器的输出端和放大器的输入端之间。 数字反馈电路被配置为提供所述第一或第二偏置电压之一。 提供电容换能器的另一个偏置电压的电压源的输出可以被低通滤波器滤波。 低通滤波器可以包括开关电容滤波器电路。
-
5.发明专利
公开(公告)号：GB2507332A
公开(公告)日：2014-04-30
申请号：GB201219335
申请日：2012-10-26
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： LESSO JOHN PAUL
Abstract: A controller 301-1 adapts the clock rate of the switched-capacitor DAC 104 in dependence on the amplitude of the audio signal. The DAC clock rate is increased for low amplitude signals, at which levels noise performance is important, in order to reduce the in-band thermal noise of the DAC. At higher signal amplitudes, where noise is less audible, the DAC clock rate is reduced to avoid distortion. The amplitude of the audio signal may be monitored by a digital level detector 302 or by an analogue level detector 303. The DAC may be of oversampling type, with an input interpolator 101. The clock rates of the word-length reduction module 102 and the dynamic element matching module 103 may also be varies in dependence on the signal amplitude.
-
Patent Agency Ranking
公开(公告)号：GB2486701B
公开(公告)日：2013-01-09
申请号：GB201021810
申请日：2010-12-23
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： LESSO JOHN PAUL , PENNOCK JOHN LAURENCE , FRITH PETER JOHN
Abstract: A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes and a second pair of output nodes, and two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes and a second bipolar output voltage at the second pair of bipolar output nodes.
-
公开(公告)号：GB2451524B
公开(公告)日：2012-11-21
申请号：GB0716917
申请日：2007-08-30
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： LESSO JOHN PAUL
IPC: H03F1/02
Abstract: An amplifier circuit comprises an input, for receiving an input signal to be amplified; a preamplifier, for amplifying the input signal based on a variable gain; a power amplifier for amplifying the signal output from the preamplifier; and a variable voltage power supply for supplying one or more supply voltages to the power amplifier. The supply voltages are adjusted based on the variable gain or the input digital signal. According to other aspects of the invention, a power supply of an amplifier circuit is clocked using a clock signal, whereby the clock signal has a frequency that varies in accordance with a volume signal or an input signal.
-
公开(公告)号：GB2488455A
公开(公告)日：2012-08-29
申请号：GB201207051
申请日：2010-12-16
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： LESSO JOHN PAUL
Abstract: In an audio amplifier, a DC offset compensation circuit is provided in which an offset compensating feedback path (107) comprises at least one voltage controlled oscillator (VCO) (108) and a counter (109). The VCO (108) provides, over time, a first VCO output signal based on the amplified output signal (Sout) and a second VCO output signal based on a reference signal (VREF). The counter (109) generates first pulse counts based upon the first VCO output signal and second pulse counts based upon the second VCO output signal and provides a compensation signal based on a comparison of the first and second pulse counts. The output signal of the counter (109) may be fed back via a DAC (112) or via digital paths (dotted). The low area occupied by the compensation circuit reduces the need to multiplex offset compensation across a large number of audio paths. In the present invention, the compensation circuitry is multiplexed between a first feedback loop for compensating offset in a first part of a signal path, and a second loop for compensating for offset in a second part of the signal path.
-
公开(公告)号：GB2484198B
公开(公告)日：2012-06-13
申请号：GB201116745
申请日：2006-08-31
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： LESSO JOHN PAUL , PENNOCK JOHN LAURENCE
IPC: H02M3/155
Abstract: A DC-DC converter circuit for generating positive and negative output voltages comprising a switch network for connecting a voltage input terminal, inductor terminal and first and second output terminals in a plurality of switching phases wherein the switch network is configured such that the maximum steady state voltage difference across a switch in any phase is not greater than the input voltage.
-
公开(公告)号：GB2485620A
公开(公告)日：2012-05-23
申请号：GB201021393
申请日：2010-12-16
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： LESSO JOHN PAUL
IPC: H03F1/30
Abstract: An amplifier (102) receives an input signal (AN) and provides an amplified output signal (Sout). A feedback path (107) provides DC offset compensation. The feedback path comprises at least one voltage controlled oscillator (VCO) (108) and a counter (109). The VCO (108) provides, over time, a first VCO output signal based on the amplified output signal (Sout) and a second VCO output signal based on a reference signal (VREF). The counter (109) generates first pulse counts based upon the first VCO output signal and second pulse counts based upon the second VCO output signal and provides a compensation signal based on a comparison of the first and second pulse counts. One voltage controlled oscillator (108) may sequentially receive a signal based on the amplifier output signal (Sout) and the reference signal (VREF) from a multiplexer (110) so as sequentially to produce the first and second VCO output signals. The output signal of the counter (109) may be fed back via a DAC (112) or via digital paths (dotted). The low area occupied by the compensation circuit reduces the need to multiplex offset compensation across a large number of audio paths.
-
-
-
-
-
-
-
-
-
Search Results
98
records
(took 0.022 seconds)
