中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

51 records (took 0.022 seconds)

    Dual output charge pump circuit having two flying capacitors
    11.
    发明专利
    Dual output charge pump circuit having two flying capacitors 未知

    公开(公告)号：GB2486701A

    公开(公告)日：2012-06-27

    申请号：GB201021810

    申请日：2010-12-23

    Applicant: WOLFSON MICROELECTRONICS PLC

    Inventor： LESSO JOHN PAUL ,  PENNOCK JOHN LAURENCE ,  FRITH PETER JOHN

    IPC: H02M1/00 ,  H02M3/07

    Abstract: A bipolar output charge pump circuit 100 is provided having a network of switching paths 110 for selectively connecting an input node VV and a reference node VG for connection to an input voltage, a first pair of output nodes VP, VN and a second pair of output nodes VQ, VM, and two pairs of flying capacitor nodes CF1A, CF1B; CF2A, CF2B, and a controller 120 for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors CF1 , CF2 connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes and a second bipolar output voltage at the second pair of bipolar output nodes.

    Amplifier circuit and methods of operation thereof
    12.
    发明专利
    Amplifier circuit and methods of operation thereof 未知

    公开(公告)号：GB2446843B

    公开(公告)日：2011-09-07

    申请号：GB0625955

    申请日：2006-12-22

    Applicant: WOLFSON MICROELECTRONICS PLC

    Inventor： LESSO JOHN PAUL ,  PENNOCK JOHN LAURENCE ,  FRITH PETER JOHN

    IPC: H03F1/02 ,  H02M3/07 ,  H03G1/00

    Abstract: A signal amplifying circuit and associated methods and apparatuses, the circuit comprising: a signal path extending from an input terminal to an output terminal, a gain controller arranged to control the gain applied along the signal path in response to a control signal; an output stage within the signal path for generating the output signal, the output stage having a gain that is substantially independent of its supply voltage, and a variable voltage power supply comprising a charge pump for providing positive and negative output voltages, the charge pump comprising a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of the states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage.

    Digital-to-analogue converter circuits
    16.
    发明专利
    Digital-to-analogue converter circuits 未知

    公开(公告)号：GB2408859B

    公开(公告)日：2007-06-06

    申请号：GB0328301

    申请日：2003-12-05

    Applicant: WOLFSON LTD ,  WOLFSON MICROELECTRONICS PLC

    Inventor： FRITH PETER JOHN ,  PENNOCK JOHN LAURENCE

    IPC: H03M3/02 ,  H03M1/66 ,  H03M3/00

    Abstract: This invention is generally concerned with digital-to-analogue converters and more particularly relates to techniques for reducing signal dependent loading of reference voltage sources used by these converters. A differential switched capacitor digital-to-analogue (DAC) circuit ( 500 ) comprises first and second differential signal circuit portions ( 500 a,b) for providing respective positive and negative signal outputs with respect to a reference level, and has first and second reference voltage inputs ( 112,114 ) for receiving respective positive and negative references. Each of said first and second circuit portions comprises an amplifier ( 102 a,b) with a feedback capacitor ( 104 a,b), a second capacitor ( 106 a,b), and a switch ( 108 a,b, 110 a,b) to switchably couple said second capacitor to a selected one of said reference voltage inputs to charge the second capacitor and to said feedback capacitor to share charge with the feedback capacitor. The switch of said first circuit portion is further configured to connect said second capacitor ( 106 a) of said first circuit portion to share charge with said feedback capacitor ( 104 b) of said second circuit portion; and the switch of said second circuit portion is further configured to connect said second capacitor ( 106 b) of said second circuit portion to share charge with said feedback capacitor ( 104 a) of said first circuit portion. This enables the second capacitors to in effect be alternately pre-charged to positive and negative signal-dependent nodes so that, on average, signal dependent loading of the references is approximately constant.

    Analogue-to-digital converter
    17.
    发明专利
    Analogue-to-digital converter 未知

    公开(公告)号：GB2502557B

    公开(公告)日：2015-09-16

    申请号：GB201209600

    申请日：2012-05-30

    Applicant: WOLFSON MICROELECTRONICS PLC

    Inventor： LESSO JOHN PAUL ,  PENNOCK JOHN LAURENCE

    IPC: H03M1/06 ,  H03M1/10 ,  H03M1/18 ,  H03M1/60

    Abstract: An apparatus and method for regulating analogue-to-digital converters. First and second input signals are received at controlled oscillator circuitry which generates respective first and second pulse streams with pulse rates based on the relevant input signal. Difference circuitry determines the difference in number of pulses of the first and second pulse streams and outputs a first digital signal. Circuitry also determines a signal independent value based on the number of pulses of the first and/or second pulse streams. In one embodiment this value is the sum or average of the number of pulses of the first and second pulse streams. This value can be used to calibrate for any variation in transfer characteristic of the oscillator circuitry. In one embodiment this value is compared to a reference value and a regulation signal passed to control circuitry to regulate the operation of the oscillation circuitry.

    Simultaneous transmission of a plurality of audio data streams via a single communication link
    18.
    发明专利
    Simultaneous transmission of a plurality of audio data streams via a single communication link 未知

    公开(公告)号：GB2497566A

    公开(公告)日：2013-06-19

    申请号：GB201121524

    申请日：2011-12-14

    Applicant: WOLFSON MICROELECTRONICS PLC

    Inventor： PENNOCK JOHN LAURENCE ,  FRITH PETER JOHN ,  LESSO JOHN PAUL

    IPC: H04S1/00 ,  H03M5/08 ,  H04L25/49 ,  H04S3/00

    Abstract: Audio interface circuitry comprises a pulse length modulator, PLM 103, for transfer of multiple digital audio data streams over a single communications link, such as a single wire. The PLM is responsive to a plurality of data streams (PDM-R, PDM-L) of 1-bit audio data samples at a sample rate, to generate a stream of data pulses (MPDM) at the sample rate. The length of each said data pulse is dependent upon on a logical combination of the current audio data samples. The PLM may also be responsive to a first clock signal having a frequency equal to the sample rate, and a second clock signal having a frequency which is a multiple of the sample rate. The length of data pulses is preferably based on a selected number of cycles of the second clock signal. Circuitry for receiving and extracting the data is also disclosed. An interface 104 receives the stream of data pulses (MPDM) and data extraction circuitry 105, 106 determines the pulse length of said data pulse and determines a data value for each of the plurality of audio data streams.

    Interface
    19.
    发明专利
    Interface 未知

    公开(公告)号：GB2489902A

    公开(公告)日：2012-10-10

    申请号：GB201214480

    申请日：2010-12-17

    Applicant: WOLFSON MICROELECTRONICS PLC

    Inventor： HATFIELD ROBERT JAMES ,  MCLEOD GORDON RICHARD ,  PENNOCK JOHN LAURENCE

    IPC: G06F13/42

    Abstract: The present invention relates to methods and apparatus for data transfer. A data interface is described with at least a first data terminal for either outputting or receiving a data signal. In bi-directional embodiments there may be one terminal for receiving data and one terminal for outputting data. A bit clock terminal outputs or receives a bit clock signal; and a frame clock terminal for outputs or receives a frame clock signal. Interface control circuitry is configurable to associate data outputted or received in each frame with time slots (1-8) of a predetermined number of bits (x, y, z) wherein the control circuitry is adapted such that the frequency of the bit clock signal can be changed at any time so as to vary the number of time slots in a frame.

Patent Agency Ranking