公开(公告)号：SG52585A1

公开(公告)日：1998-09-28

申请号：SG1996006431

申请日：1996-03-27

Applicant: YAMAHA CORP

Inventor： MAEJIMA TOSHIO

IPC: H03F3/45 ,  H03G1/00 ,  H03G3/30

Abstract: An automatic gain control circuit is provided, which has minimum variations in the output signal level even with the presence of variations in component parts thereof and the temperature dependency of component parts thereof and can therefore dispense with the use of an additional amplifier circuit for adjusting the output level. An input signal-attenuating circuit attenuates the level of an input signal to a voltage amplifier circuit. An output level-detecting circuit detects the voltage level of an output signal from the voltage amplifier circuit to thereby carry out feedback control by controlling the attenuating characteristic of the input signal-attenuating circuit in response to the detected voltage of the output signal such that the voltage level of the output signal from the voltage amplifier circuit is maintained at a constant level. The output level-detecting circuit is comprised of a differential amplifier circuit which detects and amplifies the difference between a predetermined reference voltage and the voltage of the output signal from the voltage amplifier circuit.

公开(公告)号：EP1239585A4

公开(公告)日：2005-09-14

申请号：EP00978050

申请日：2000-12-01

Applicant: YAMAHA CORP

Inventor： MAEJIMA TOSHIO

IPC: H03F3/30 ,  H03F3/45

CPC classification number: H03F3/45179 ,  H03F3/3028 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45292 ,  H03F2203/45651

Abstract: A differential amplifier circuit comprises an input circuit (10) for generating the difference in voltage between a positive input signal and a negative input signal; a feedback bias circuit (20) for providing a bias voltage corresponding to the differential voltage signal in response to the differential voltage signal supplied by the input circuit (10) and for feeding the output current back to control the bias voltage; an output circuit (30) for supplying load with the output current corresponding to the bias voltage; and a current detector circuit (40) for detecting the output current and supplying it to the feedback bias circuit (20). The differential amplifier circuit performs as a class-AB amplifier with the bias current value being close to zero if the differential voltage signal is zero.

公开(公告)号：JP2012210062A

公开(公告)日：2012-10-25

申请号：JP2011073734

申请日：2011-03-29

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KAWAGISHI NORIHIRO ,  TSUJI NOBUAKI ,  MAEJIMA TOSHIO

IPC: H02M3/155

Abstract: PROBLEM TO BE SOLVED: To suppress power supply noise even when a load is reduced.SOLUTION: A voltage generation circuit 100 supplies an activating driving pulse PDR1 to a transistor TR1 connected to a DC power supply to generate an output voltage VOUT. A comparison circuit 50 generates a control signal CTL that becomes active for a period depending on the magnitude of an error signal Err. A drive circuit 80 controls the P channel transistor TR1 and an N channel transistor TR2 on/off according to the active period of the control signal CTL and a reference time Tref. A reset signal generation circuit 60 controls the frequency of the control signal CTL within a range from a lower limit frequency fmin to an upper limit frequency fmax.

Abstract translation: 要解决的问题：即使当负载减小时也抑制电源噪声。 解决方案：电压产生电路100将激活驱动脉冲PDR1提供给连接到直流电源的晶体管TR1，以产生输出电压VOUT。 比较电路50根据误差信号Err的大小产生一段时间变为有效的控制信号CTL。 驱动电路80根据控制信号CTL的有效期和基准时间Tref，控制P沟道晶体管TR1和N沟道晶体管TR2的导通/截止。 复位信号生成电路60在从下限频率fmin到上限频率fmax的范围内控制控制信号CTL的频率。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2011066558A

公开(公告)日：2011-03-31

申请号：JP2009213806

申请日：2009-09-15

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KISHII TATSUYA ,  IYODA MORITAKA ,  TSUCHIYA HIROTOSHI ,  MAEJIMA TOSHIO ,  NAKAMURA KATSUYOSHI ,  MIYAZAKI MASAHITO ,  HIMENO AKIHISA

IPC: H03F3/217 ,  H03F1/00

CPC classification number: H03F3/217

Abstract: PROBLEM TO BE SOLVED: To achieve a mute function of a class-D amplifier without making a circuit large in scale nor complicated. SOLUTION: An output limit instruction generating section 310 detects that output digital signals VOp and VOn are clipped, and outputs an output limit instruction signal Cdet. An attenuation instruction pulse generating section 320 includes a capacitor C30 for integrating the output limit instruction signal Cdet, and outputs a periodical attenuation instruction pulse SW having pulse width corresponding to a voltage VC1 of the capacitor C30. An attenuator 160 is provided in an input path for input signals VIp and VIn to the class-D amplifier, and turns on by being supplied with the attenuation instruction pulse SW to attenuate the input signals. A mute control section 330 controls the voltage VC1 of the capacitor C30 independently of the output limit instruction signal Cdet to control an amount of the attenuation applied by the attenuator 160 applied to the input signal. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为了实现D类放大器的静音功能，而不会使电路规模大，也不复杂。 解决方案：输出限制指令生成部分310检测输出数字信号VOp和VOn被剪切，并输出输出限制指令信号Cdet。 衰减指令脉冲发生部分320包括用于积分输出限制指令信号Cdet的电容器C30，并且输出具有与电容器C30的电压VC1相对应的脉冲宽度的周期性衰减指令脉冲SW。 衰减器160设置在D类放大器的输入信号VIp和VIn的输入路径中，并通过提供衰减指令脉冲SW来导通，以衰减输入信号。 静音控制部分330独立于输出限制指令信号Cdet控制电容器C30的电压VC1，以控制施加到输入信号的衰减器160施加的衰减量。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2006128787A

公开(公告)日：2006-05-18

申请号：JP2004310989

申请日：2004-10-26

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MAEJIMA TOSHIO

IPC: H03F3/217 ,  H03F1/26

Abstract: PROBLEM TO BE SOLVED: To provide a class D amplifier capable of preventing output noise generated by a switching operation.
SOLUTION: An integrating circuit 16 integrates the difference between an input signal through a resistor 12 and a feedback signal through a resistor 13. A triangular wave generator 17 generates the triangular wave of a constant period. A comparator 18 compares the output of the integrating circuit 16 with the output of the triangular wave generator 17, and outputs a result of the comparison. A pulse width modulation signal is generated by this comparator 18. A delay circuit 30 delays the output of the comparator 18 for a predetermined time and outputs the delayed output. A buffer amplifier 19 amplifies the output of the delay circuit 30, adds the amplified output to an output terminal 20, and feeds the output back to an input side of the integrating circuit 16 via the resistor 13. With the provided delay circuit 30, a switching noise generated in the comparator 18 is delayed and returned to the input side, thereby preventing the output noise.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供能够防止由开关操作产生的输出噪声的D类放大器。 解决方案：积分电路16通过电阻器12将通过电阻器12的输入信号和反馈信号之间的差积分起来。三角波发生器17产生恒定周期的三角波。 比较器18将积分电路16的输出与三角波发生器17的输出进行比较，并输出比较结果。 脉冲宽度调制信号由该比较器18产生。延迟电路30将比较器18的输出延迟预定时间并输出延迟的输出。 缓冲放大器19放大延迟电路30的输出，将放大的输出与输出端子20相加，并通过电阻器13将输出反馈给积分电路16的输入端。利用所提供的延迟电路30， 在比较器18中产生的开关噪声被延迟并返回到输入侧，从而防止输出噪声。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004208216A

公开(公告)日：2004-07-22

申请号：JP2002377818

申请日：2002-12-26

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MAEJIMA TOSHIO

IPC: H03F3/217

Abstract: PROBLEM TO BE SOLVED: To eliminate a DC offset by reducing a manufacturing cost.
SOLUTION: A comparator CMP compares pulse width modulation outputs on both sides, to generate a duty pulse whose signal level is lowered by a pulse train of the same shape as the output. An integration circuit 4 smooths a duty deviation of the duty pulse, being the DC offset, contained in the modulation output, to output a signal on a level proportional to the DC offset. An adder 5 adds the signal on the level proportional to the DC offset to an input signal INO to make an input signal IN to an Lch pulse width modulator/amplifier part 1. For example, when the DC offset on a positive level is included in the pulse width modulation output, a signal on a negative level is outputted from the integration circuit 4. Thereby, since the level of the input signal IN falls, a duty ratio of the pulse width modulation outputs on each side is corrected in a decrease direction.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2000022472A

公开(公告)日：2000-01-21

申请号：JP18086498

申请日：1998-06-26

Applicant: YAMAHA CORP

Inventor： MAEJIMA TOSHIO ,  NORO MASAO

IPC: H03G7/00 ,  H03G3/30

Abstract: PROBLEM TO BE SOLVED: To provide an amplitude compressor that is easily integrated into an IC in a MOS process. SOLUTION: When an input signal Vin is fed to a PWM modulation section 10, the input signal Vin is PWM-modulated depending on a modulation degree decided by a control signal Cs and a PWM modulation signal Vm is generated. An amplitude detection section 30 detects an amplitude of an output signal Vout based on a signal V' that is an inverse of the PWM modulation signal Vm to generate the control signal Cs in response to the detection result. Since the control signal Cs is given as positive and negative power supplies vh, vl of a buffer 13, a feedback amount of an operational amplifier 11 is adjusted thereby to adjust a modulation degree of the PWM modulation signal Vm. A demodulation section 20 demodulates the PWM modulation signal Vm to generate the output signal Vout.

公开(公告)号：JP2014212421A

公开(公告)日：2014-11-13

申请号：JP2013087362

申请日：2013-04-18

Applicant: ヤマハ株式会社 ,  Yamaha Corp

Inventor： MAEJIMA TOSHIO

IPC: H03M1/12

CPC classification number: H03M1/12

Abstract: 【課題】差動形式で入力信号を増幅する場合に、容量素子のばらつきを補正して正確なデジタル信号に変換する。【解決手段】AD変換装置1は、差動増幅部10を備える。補正モードの第1期間において、容量素子11及び21は電荷を放電し、容量素子12には低基準電圧VREFNと基準電圧VREFが印加され、容量素子22には高基準電圧VREFPと基準電圧VREFが印加される。第2期間において、容量素子11の一方の電極に低基準電圧VREFNを供給し、容量素子21の一方の電極に高基準電圧VREFPを供給する。これによって、容量値の比に応じて容量素子11及び12の間、容量素子21及び22の間で電荷が移動する。このため、負出力信号S1及び正出力信号S2は、容量値の比を反映したものとなる。【選択図】図1

Abstract translation: 要解决的问题：为了在以差分模式放大输入信号时产生补偿电容元件变化的精确数字信号转换。解决方案：AD转换装置1包括差分放大部分10.在补偿模式的第一周期中， 电容元件11和21被电放电，将低参考电压VREFN和参考电压VREF施加到电容元件12，并且将高参考电压VREFP和参考电压VREF施加到电容元件22.在第二周期 ，将低参考电压VREFN提供给电容元件11的一个电极，并且将高参考电压VREFP提供给电容元件21的一个电极。这将使电容元件11和12之间以及电容元件11之间的电荷 元件21和22根据电容值比。 因此，负输出信号S1和正输出信号S2反映电容值比。

公开(公告)号：JP2014089087A

公开(公告)日：2014-05-15

申请号：JP2012238456

申请日：2012-10-30

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MIYAZAKI MASAHITO ,  MAEJIMA TOSHIO

IPC: G01R33/09 ,  G01D5/12 ,  G01D5/244 ,  H01L43/06 ,  H01L43/08

CPC classification number: H03K5/003

Abstract: PROBLEM TO BE SOLVED: To allow appropriate cancellation of an offset voltage due to variance among individual resistance elements constituting a bridge circuit, without being affected by temperature characteristics of respective resistance elements.SOLUTION: An offset canceling circuit 9 includes: an operational amplifier 11 which has a first resistance 13 inserted to a negative feedback line thereof and amplifies a first output signal Sa from a bridge resistance type sensor 3 and outputs the amplification result; an operational amplifier 12 which has a second resistance 14 inserted to a negative feedback line thereof and amplifies a second output signal Sb from the bridge resistance type sensor 3 and outputs the amplification result; a third resistance 15 connected between respective inverted input terminals of the operational amplifiers 11 and 12; and a current source 6 which causes a constant current to flow to the third resistance 15. The current source 6 causes a constant current I, corresponding to an offset voltage Voff included in the first and second output signals Sa and Sb from the bridge resistance type sensor 3, to flow to the third resistance 15, and the offset voltage Voff is thereby canceled from the output signals of the operational amplifiers 11 and 12.

Abstract translation: 要解决的问题：不受各个电阻元件的温度特性的影响，允许由构成桥接电路的各个电阻元件之间的变化引起的偏移电压的适当消除。解决方案：偏移消除电路9包括：运算放大器11， 具有插入其负反馈线的第一电阻13并从桥电阻型传感器3放大第一输出信号Sa并输出放大结果; 运算放大器12，其具有插入其负反馈线的第二电阻14，并从桥电阻型传感器3放大第二输出信号Sb，并输出放大结果; 连接在运算放大器11和12的各个反相输入端之间的第三电阻15; 以及导致恒定电流流向第三电阻15的电流源6.电流源6产生对应于来自桥电阻型的第一和第二输出信号Sa和Sb中包括的偏移电压Voff的恒定电流I 传感器3流向第三电阻15，从而从运算放大器11和12的输出信号中消除偏移电压Voff。

公开(公告)号：JP2009100602A

公开(公告)日：2009-05-07

申请号：JP2007271844

申请日：2007-10-18

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MIYAZAKI MASAHITO ,  MAEJIMA TOSHIO

IPC: H02M3/155

CPC classification number: H02M3/158

Abstract: PROBLEM TO BE SOLVED: To provide a DC-DC converter capable of extinguishing in a short time the energy stored in an inductor for forming a resonance circuit during switching output resonance without enlarging a circuit scale.
SOLUTION: The DC-DC converter includes: a switching element for switching an inputted DC power supply voltage; an LC low pass filter formed of the inductor and a capacitor connected to an output end of the switching element; and a control means for controlling the timing of on/off operation of the switching element so that an output voltage of the LC low pass filter becomes a predetermined voltage. In this converter, between both ends of the inductor constituting the LC low pass filter, a series circuit consisting of a resistance element and a switching means is parallel-connected, and the control means controls the switching means to be closed during resonance of the LC low pass filter.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种DC-DC转换器，其能够在短时间内熄灭存储在电感器中的能量，用于在切换输出谐振期间形成谐振电路，而不增加电路规模。 解决方案：DC-DC转换器包括：用于切换输入的直流电源电压的开关元件; 由电感器形成的LC低通滤波器和连接到开关元件的输出端的电容器; 以及控制装置，用于控制开关元件的开/关操作的定时，使得LC低通滤波器的输出电压变为预定电压。 在该转换器中，在构成LC低通滤波器的电感器的两端之间并联连接由电阻元件和开关装置构成的串联电路，控制装置控制开关装置在LC谐振期间闭合 低通滤波器。 版权所有（C）2009，JPO＆INPIT