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公开(公告)号：US20230183060A1
公开(公告)日：2023-06-15
申请号：US18072506
申请日：2022-11-30
Applicant: SiTime Corporation
Inventor： Charles I. Grosjean , Nicholas Miller , Paul M. Hagelin , Ginel C. Hill , Joseph C. Doll
CPC classification number: B81C1/00698 , H03H3/0073 , H03H9/1057 , H10N30/05 , H10N39/00 , B81C1/00158 , B81C2201/0171
Abstract: Multiple degenerately-doped silicon layers are implemented within resonant structures to control multiple orders of temperature coefficients of frequency.
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12.发明授权Temperature compensation in a semiconductor micromechanical resonator via charge carrier depletion 有权通过电荷载流子耗尽在半导体微机械谐振器中的温度补偿公开(公告)号：US09319020B2
公开(公告)日：2016-04-19
申请号：US13276931
申请日：2011-10-19
Applicant: Farrokh Ayazi , Ashwin Samarao
Inventor： Farrokh Ayazi , Ashwin Samarao
CPC classification number: H03H3/0076 , B81B3/0081 , B81C2201/0171 , H03H9/02448 , H03H9/2463 , H03H2009/02496 , H03H2009/2415
Abstract: A semiconductor resonator has a substrate with a thickness extending between a first end and a second end and a pn-junction along the thickness of the substrate forming a free charge carrier depletion region. In another embodiment, a semiconductor resonator has a substrate with a crystal lattice doped at degenerate levels such that the flow of free charge carriers can be minimized. A method of compensating a temperature coefficient of a semiconductor resonator by creating a pn-junction based free charge carrier depletion region within a thickness of a substrate of the resonator is also disclosed.
Abstract translation: 半导体谐振器具有在第一端和第二端之间延伸的厚度的衬底和沿衬底的厚度的pn结，形成自由电荷载流子耗尽区。 在另一个实施例中，半导体谐振器具有在退化水平下掺杂晶格的衬底，使得自由电荷载流子的流动可以最小化。 还公开了通过在共振器的衬底的厚度内产生基于pn结的自由电荷载流子耗尽区域来补偿半导体谐振器的温度系数的方法。
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公开(公告)号：US20150235779A1
公开(公告)日：2015-08-20
申请号：US14182839
申请日：2014-02-18
Applicant: Analog Devices Global
Inventor： Check F. Lee , Raymond C. Goggin , Padraig L. Fitzgerald
CPC classification number: H01H1/0036 , B81B7/0064 , B81B2201/014 , B81B2207/03 , B81B2207/07 , B81B2207/115 , B81C1/00698 , B81C2201/0171 , B81C2203/075 , H01H59/0009 , H01P1/127
Abstract: A MEMS apparatus has a substrate, an input node, an output node, and a MEMS switch between the input node and the output node. The switch selectively connects the input node and the output node, which are electrically isolated when the switch is open. The apparatus also has an input doped region in the substrate and an output doped region in the substrate. The input doped region and output doped region are electrically isolated through the substrate—i.e., the resistance between them inhibits non-negligible current flows between the two doped regions. The input doped region forms an input capacitance with the input node, while the output doped region forms an output capacitance with the output node.
Abstract translation: MEMS装置在输入节点和输出节点之间具有衬底，输入节点，输出节点和MEMS开关。 开关选择性地连接输入节点和输出节点，当开关打开时，输出节点和输出节点电隔离。 该装置还具有衬底中的输入掺杂区域和衬底中的输出掺杂区域。 输入掺杂区域和输出掺杂区域通过衬底电隔离，即它们之间的电阻在两个掺杂区域之间抑制不可忽略的电流。 输入掺杂区域与输入节点形成输入电容，而输出掺杂区域与输出节点形成输出电容。
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14.发明申请Temperature Compensation in a Semiconductor Micromechanical Resonator Via Charge Carrier Depletion 有权半导体微机械谐振器中的温度补偿通过电荷载体耗尽公开(公告)号：US20130099629A1
公开(公告)日：2013-04-25
申请号：US13276931
申请日：2011-10-19
Applicant: Farrokh Ayazi , Ashwin Samarao
Inventor： Farrokh Ayazi , Ashwin Samarao
IPC: H01L41/04
CPC classification number: H03H3/0076 , B81B3/0081 , B81C2201/0171 , H03H9/02448 , H03H9/2463 , H03H2009/02496 , H03H2009/2415
Abstract: A semiconductor resonator has a substrate with a thickness extending between a first end and a second end and a pn-junction along the thickness of the substrate forming a free charge carrier depletion region. In another embodiment, a semiconductor resonator has a substrate with a crystal lattice doped at degenerate levels such that the flow of free charge carriers can be minimized. A method of compensating a temperature coefficient of a semiconductor resonator by creating a pn-junction based free charge carrier depletion region within a thickness of a substrate of the resonator is also disclosed.
Abstract translation: 半导体谐振器具有在第一端和第二端之间延伸的厚度的衬底和沿衬底的厚度的pn结，形成自由电荷载流子耗尽区。 在另一个实施例中，半导体谐振器具有在退化水平下掺杂晶格的衬底，使得自由电荷载流子的流动可以最小化。 还公开了通过在共振器的衬底的厚度内产生基于pn结的自由电荷载流子耗尽区域来补偿半导体谐振器的温度系数的方法。
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15.发明申请METHODS AND SYSTEMS FOR CHEMICALLY ENCODING HIGH-RESOLUTION SHAPES IN SILICON NANOWIRES 审中-公开用于化学编码硅纳米线中的高分辨率形状的方法和系统
公开(公告)号：WO2014179340A2
公开(公告)日：2014-11-06
申请号：PCT/US2014/035920
申请日：2014-04-29
Inventor： CAHOON, James , CHRISTESEN, Joseph , PINION, Christopher
CPC classification number: H01L29/0673 , B81B3/0021 , B81B2203/0118 , B81B2203/0361 , B81C1/00111 , B81C1/0015 , B81C2201/013 , B81C2201/0171 , B81C2201/0176 , G01Q60/38 , H01L21/02238 , H01L21/02255 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02603 , H01L21/0262 , H01L21/283 , H01L21/30604 , H01L29/16 , H01L31/028 , H01L31/035281 , H01L31/03529 , H01L31/09 , Y02E10/50
Abstract: Methods of chemically encoding high-resolution shapes in silicon nanowires during metal nanoparticle catalyzed vapor-liquid-solid growth or vapor-solid-solid growth are provided. In situ phosphorus or boron doping of the silicon nanowires can be controlled during the growth of the silicon nanowires such that high-resolution shapes can be etched along a growth axis on the silicon nanowires. Nanowires with an encoded morphology can have high-resolution shapes with a size resolution of about 1,000 nm to about 10 nm and comprise geometrical shapes, conical profiles, nanogaps and gratings.
Abstract translation: 提供了在金属纳米粒子催化的气 - 液 - 固 - 固生长或蒸气固 - 固生长期间化学编码硅纳米线中的高分辨率形状的方法。 硅纳米线的原位磷掺杂或硼掺杂可以在硅纳米线生长期间被控制，使得高分辨率形状可以沿着硅纳米线上的生长轴被蚀刻。 具有编码形态的纳米线可以具有尺寸分辨率为约1,000nm至约10nm的高分辨率形状，并且包括几何形状，圆锥形轮廓，纳米间隙和光栅。
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Patent Agency Ranking
公开(公告)号：WO2009096961A1
公开(公告)日：2009-08-06
申请号：PCT/US2008/052476
申请日：2008-01-30
Inventor： WANG, Shih-Yuan , TAN, Michael, Renne Ty
CPC classification number: B81C1/00142 , B81C2201/0171 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L31/035281 , H01L31/105 , H01L2924/0002 , Y02E10/50 , H01L2924/00
Abstract: A nanostructure (10, 10', 10', 10'') includes a highly conductive microcrystalline layer (18), a bipolar nanowire (16) and another layer (18, 30). The highly conductive microcrystalline layer (18) includes a microcrystalline material and a metal. The bipolar nanowire (16) has one end attached to the highly conductive microcrystalline layer (18) and another end attached to the other layer (18, 30).
Abstract translation: 纳米结构（10,10'，10“，10”）包括高导电性微晶层（18），双极纳米线（16）和另一层（18,30）。 高导电性微晶层（18）包括微晶材料和金属。 双极纳米线（16）的一端连接到高导电微晶层（18），另一端连接到另一层（18,30）。
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公开(公告)号：US12095447B1
公开(公告)日：2024-09-17
申请号：US16591717
申请日：2019-10-03
Applicant: SiTime Corporation
Inventor： Charles I. Grosjean , Ginel C. Hill , Paul M. Hagelin , Renata Melamud Berger , Aaron Partridge , Markus Lutz
CPC classification number: H03H9/2457 , B81C1/0069 , H03H3/0072 , H03H3/0076 , H03H9/1057 , B81C2201/0164 , B81C2201/0171
Abstract: A microelectromechanical system (MEMS) resonator includes a substrate having a substantially planar surface and a resonant member having sidewalls disposed in a nominally perpendicular orientation with respect to the planar surface. Impurity dopant is introduced via the sidewalls of the resonant member such that a non-uniform dopant concentration profile is established along axis extending between the sidewalls parallel to the substrate surface and exhibits a relative minimum concentration in a middle region of the axis.
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公开(公告)号：US11975965B2
公开(公告)日：2024-05-07
申请号：US18340815
申请日：2023-06-23
Applicant: SiTime Corporation
Inventor： Charles I. Grosjean , Nicholas Miller , Paul M. Hagelin , Ginel C. Hill , Joseph C. Doll
CPC classification number: B81C1/00698 , H03H3/0073 , H03H9/1057 , H10N30/05 , H10N39/00 , B81C1/00158 , B81C2201/0171
Abstract: Multiple degenerately-doped silicon layers are implemented within resonant structures to control multiple orders of temperature coefficients of frequency.
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公开(公告)号：US11724934B2
公开(公告)日：2023-08-15
申请号：US18072506
申请日：2022-11-30
Applicant: SiTime Corporation
Inventor： Charles I. Grosjean , Nicholas Miller , Paul M. Hagelin , Ginel C. Hill , Joseph C. Doll
CPC classification number: B81C1/00698 , H03H3/0073 , H03H9/1057 , H10N30/05 , H10N39/00 , B81C1/00158 , B81C2201/0171
Abstract: Multiple degenerately-doped silicon layers are implemented within resonant structures to control multiple orders of temperature coefficients of frequency.
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公开(公告)号：US09659717B2
公开(公告)日：2017-05-23
申请号：US14182839
申请日：2014-02-18
Applicant: Analog Devices Global
Inventor： Check F. Lee , Raymond C. Goggin , Padraig L. Fitzgerald
CPC classification number: H01H1/0036 , B81B7/0064 , B81B2201/014 , B81B2207/03 , B81B2207/07 , B81B2207/115 , B81C1/00698 , B81C2201/0171 , B81C2203/075 , H01H59/0009 , H01P1/127
Abstract: A MEMS apparatus has a substrate, an input node, an output node, and a MEMS switch between the input node and the output node. The switch selectively connects the input node and the output node, which are electrically isolated when the switch is open. The apparatus also has an input doped region in the substrate and an output doped region in the substrate. The input doped region and output doped region are electrically isolated through the substrate—i.e., the resistance between them inhibits non-negligible current flows between the two doped regions. The input doped region forms an input capacitance with the input node, while the output doped region forms an output capacitance with the output node.
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