公开(公告)号：US11943939B2

公开(公告)日：2024-03-26

申请号：US17140441

申请日：2021-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Kai Hsu ,  Jerry Chang Jui Kao ,  Chin-Shen Lin ,  Ming-Tao Yu ,  Tzu-Ying Lin ,  Chung-Hsing Wang

IPC: H10K19/10 ,  H01L21/822 ,  H01L27/06 ,  H01L49/02 ,  H10K19/00

CPC classification number: H10K19/10 ,  H01L21/822 ,  H01L27/0688 ,  H01L28/10 ,  H01L28/40 ,  H10K19/201

Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.

公开(公告)号：US11793009B2

公开(公告)日：2023-10-17

申请号：US17979904

申请日：2022-11-03

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： Yukio Kaneda ,  Fumihiko Koga

IPC: H10K39/32 ,  H04N23/84 ,  H04N25/00 ,  H04N25/79 ,  H10K30/81 ,  H01L27/146 ,  H10K19/00

CPC classification number: H10K39/32 ,  H04N23/84 ,  H04N25/00 ,  H04N25/79 ,  H10K30/81 ,  H01L27/14647 ,  H10K19/201

Abstract: An imaging device includes a first electrode, a charge accumulating electrode arranged with a space from the first electrode, an isolation electrode arranged with a space from the first electrode and the charge accumulating electrode and surrounding the charge accumulating electrode, a photoelectric conversion layer formed in contact with the first electrode and above the charge accumulating electrode with an insulating layer interposed therebetween, and a second electrode formed on the photoelectric conversion layer. The isolation electrode includes a first isolation electrode and a second isolation electrode arranged with a space from the first isolation electrode, and the first isolation electrode is positioned between the first electrode and the second isolation electrode.

公开(公告)号：US20230307553A1

公开(公告)日：2023-09-28

申请号：US18324638

申请日：2023-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong Heo ,  Taehwan Moon ,  Hagyoul Bae ,  Seunggeol Nam ,  Sangwook Kim ,  Kwanghee Lee

IPC: H01L29/86 ,  H10K10/50 ,  H10K19/00 ,  H10B69/00

CPC classification number: H01L29/86 ,  H10K10/50 ,  H10K19/00 ,  H10K19/201 ,  H10B69/00

Abstract: A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

公开(公告)号：US20230403868A1

公开(公告)日：2023-12-14

申请号：US18447614

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jerry Chang Jui KAO ,  Meng-Kai HSU ,  Chin-Shen LIN ,  Ming-Tao YU ,  Tzu-Ying LIN ,  Chung-Hsing WANG

IPC: H10K19/10 ,  H10K19/00

CPC classification number: H10K19/10 ,  H01L28/10 ,  H01L28/40 ,  H10K19/201

Abstract: A method includes forming a circuit region over a substrate. The circuit region includes at least one active region extending along a first direction, and at least one gate region extending across the at least one active region and along a second direction transverse to the first direction. At least one first input/output (TO) pattern and at least one second TO pattern are correspondingly formed in different first and second metal layers to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first TO pattern extends along a third direction oblique to both the first direction and the second direction. The at least one second TO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction.

公开(公告)号：US11799438B2

公开(公告)日：2023-10-24

申请号：US17322187

申请日：2021-05-17

Applicant: Infineon Technologies AG

Inventor： Alexander Schade ,  Sergey Miropolskiy

IPC: H03H7/09 ,  H03H1/00 ,  H10K39/00 ,  H10K19/10 ,  H10K19/00 ,  H03H7/06

CPC classification number: H03H7/09 ,  H03H1/0007 ,  H03H7/06 ,  H10K19/10 ,  H10K19/201 ,  H10K39/00

Abstract: An integrated circuit including a first circuit module and a second circuit module is provided. A layer stack may include one or multiple metal layers with a power segment and a ground segment connected to the first circuit module and the second circuit module, which form a resonant current loop. A pickup loop may be inductively coupled to the resonant current loop to dampen its resonance, thereby making the IC compliant with its EMC requirements or removing functional errors such as problems in the signal or power integrity.

公开(公告)号：US20230292536A1

公开(公告)日：2023-09-14

申请号：US18303074

申请日：2023-04-19

Applicant: SONY GROUP CORPORATION

Inventor： Tetsuji YAMAGUCHI ,  Atsushi TODA ,  Itaru OSHIYAMA

IPC: H10K39/32 ,  H01L27/146 ,  H01L31/10 ,  G02B5/20 ,  H04N23/11 ,  H04N23/12 ,  H04N25/79 ,  H10K19/20 ,  H10K19/00

CPC classification number: H10K39/32 ,  G02B5/201 ,  G02B5/208 ,  H01L27/146 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/1464 ,  H01L27/14649 ,  H01L27/14667 ,  H01L31/10 ,  H04N23/11 ,  H04N23/12 ,  H04N25/79 ,  H10K19/20 ,  H10K19/201 ,  H04N25/75

Abstract: A solid-state imaging apparatus includes a pixel array part in which a plurality of pixels are two-dimensionally arranged, in which each pixel has a first photoelectric conversion region formed above a semiconductor layer, a second photoelectric conversion region formed in the semiconductor layer, a first filter configured to transmit a light in a predetermined wavelength region corresponding to a color component, and a second filter having different transmission characteristics from the first filter, one photoelectric conversion region out of the first photoelectric conversion region and the second photoelectric conversion region photoelectrically converts a light in a visible light region, the other photoelectric conversion region photoelectrically converts a light in an infrared region, the first filter is formed above the first photoelectric conversion region, and the second filter has transmission characteristics of making wavelengths of lights in an infrared region absorbed in the other photoelectric conversion region formed below the first filter the same.

公开(公告)号：US11723222B2

公开(公告)日：2023-08-08

申请号：US17074848

申请日：2020-10-20

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato ,  Bomy Chen

IPC: H10K19/00 ,  H10K19/10 ,  H01L49/02

CPC classification number: H10K19/201 ,  H10K19/10 ,  H01L28/10

Abstract: An integrated circuit (IC) package product, e.g., system-on-chip (SoC) or system-in-package (SiP) product, may include at least one integrated inductor having a core magnetic field (B field) that extends parallel to the substrate major plane of at least one die or chiplet included in or mounted to the product, which may reduce the eddy currents within each die/chiplet substrate, and thereby reduce energy loss of the indictor. The IC package product may include a horizontally-extending IC package substrate, a horizontally-extending die mount base arranged on the IC package substrate, at least one die mounted to the die mount base in a vertical orientation, and an integrated inductor having a B field extending in a vertical direction parallel to the silicon substrate of each vertically-mounted die, thereby providing a reduced substrate loss in the integrated inductor, which provides an increased quality factor (Q) of the inductor.