中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

4906 records (took 0.048 seconds)

    EEPROM COMPRISING A NON-VOLATILE REGISTER WHICH IS INTEGRATED INTO THE MEMORY AREA THEREOF
    191.
    发明申请
    EEPROM COMPRISING A NON-VOLATILE REGISTER WHICH IS INTEGRATED INTO THE MEMORY AREA THEREOF 审中-公开
    包含一个非易失性寄存器的EEPROM集成到其内存区域

    公开(公告)号：WO2004021361A3

    公开(公告)日：2004-07-29

    申请号：PCT/FR0302559

    申请日：2003-08-21

    Applicant: ST MICROELECTRONICS SA ,  LA ROSA FRANCESCO

    Inventor： LA ROSA FRANCESCO

    IPC: G11C16/04 ,  G11C16/06 ,  H01L21/8247 ,  H01L27/115 ,  G11C16/20

    CPC classification number: H01L27/11521 ,  G11C16/0441 ,  H01L27/115 ,  H01L27/11524

    Abstract: The invention relates to an electrically erasable programmable memory which is integrated onto a silicon substrate, comprising a memory area consisting of normal bit lines (BLj) and normal memory cells (C(i, j)) which are connected to the aforementioned normal bit lines (BLj). Each normal memory cell consists of a floating gate transistor (FGT) comprising a tunnel window (TW) and a selection transistor (ST). According to the invention, the memory area (MA) includes at least one memory point of a non-volatile register (NVREG), comprising: a normal memory cell (C(i+1, j) which is connected to a normal bit line (BLj) of the memory area and which can be erased and programmed using decoders (RDEC, CDEC) of the memory area; a special memory cell C(i+1, j+1) comprising a floating gate transistor (FGT) without a tunnel window, the floating gate of the floating gate transistor of the special memory cell being connected to the floating gate of the floating gate transistor of the normal memory cell; and a special bit line (RBL+1) which is used to connect the special memory cell of the memory point to a specific read-out circuit of the memory point.

    Abstract translation: 本发明涉及一种电可擦除可编程存储器，其集成在硅衬底上，包括由正常位线（BLj）和正常存储单元（C（i，j））组成的存储区域，其连接到上述正常位线 （BLJ）的。 每个正常存储单元由包括隧道窗（TW）和选择晶体管（ST）的浮栅晶体管（FGT）组成。 根据本发明，存储区（MA）包括非易失性寄存器（NVREG）的至少一个存储点，包括：正常存储器单元（C（i + 1，j），其连接到正常位线 （BLj），并且可以使用存储器区域的解码器（RDEC，CDEC）来擦除和编程;特殊存储单元C（i + 1，j + 1），包括不具有 特殊存储单元的浮栅晶体管的浮栅与正常存储单元的浮栅晶体管的浮置栅极相连，特殊位线（RBL + 1）用于连接特殊存储单元 存储器的存储单元指向存储点的特定读出电路。

    ASYNCHRONOUS DATA RECEIVER COMPRISING MEANS FOR STANDBY MODE SWITCHOVER
    193.
    发明申请
    ASYNCHRONOUS DATA RECEIVER COMPRISING MEANS FOR STANDBY MODE SWITCHOVER 审中-公开
    包含待机模式开关的手段的异步数据接收器

    公开(公告)号：WO03034247A3

    公开(公告)日：2003-09-25

    申请号：PCT/FR0203479

    申请日：2002-10-11

    Applicant: ST MICROELECTRONICS SA ,  RUAT LUDOVIC ,  KINOWSKI PAUL ,  CZAJOR ALEXANDER

    Inventor： RUAT LUDOVIC ,  KINOWSKI PAUL ,  CZAJOR ALEXANDER

    IPC: G06F13/38

    CPC classification number: G06F13/385

    Abstract: The invention concerns a device (UART1) for receiving asynchronous frames starting with a header field (BRK, SYNC, CH1), comprising means (SMI, WU) for standby mode switchover, header field identifying means (SMI), and means (SMI) for switching from standby mode when a valid header field is identified, the standby mode including filtering of at least one signal (DRC) capable of being transmitted by the receiver device during reception of a header field. The invention is in particular applicable to UART circuits present in microcontrollers.

    Abstract translation: 本发明涉及用于从头字段（BRK，SYNC，CH1）开始接收异步帧的装置（UART1），包括用于待机模式切换的装置（SMI，WU），头字段识别装置（SMI）和装置（SMI） 用于在识别有效标题字段时从待机模式切换，所述待机模式包括在接收标题字段期间能够由接收机设备发送的至少一个信号（DRC）的过滤。 本发明特别适用于存在于微控制器中的UART电路。

    METHOD FOR MAKING SECURE A SECRET QUANTITY
    194.
    发明申请
    METHOD FOR MAKING SECURE A SECRET QUANTITY 审中-公开
    确保安全数量的方法

    公开(公告)号：WO03024017A2

    公开(公告)日：2003-03-20

    申请号：PCT/FR0203007

    申请日：2002-09-04

    Applicant: ST MICROELECTRONICS SA ,  SAGEM ,  LIARDET PIERRE-YVAN ,  CHABANNE HERVE

    Inventor： LIARDET PIERRE-YVAN ,  CHABANNE HERVE

    IPC: H04L9/10 ,  H04L9/06

    CPC classification number: H04L9/0625 ,  G06F2207/7219 ,  H04L9/004

    Abstract: The invention concerns a method and a system for making secure a secret quantity, contained in an electronic device, and used at least partly in an encryption algorithm of at least part of an input data executing a predetermined number (N) of successive iterations of a common function and producing at least part of an output data, which consists in: storing (14), after a first number (X) of iterations, an intermediate result; applying, to the output data, a function inverse to that of the encryption for a number (N-X) of iterations corresponding to the difference between the total number of iterations and the first number; comparing (18) the intermediate result with the result of iterations of the inverse function; and validating the encryption only if the two results are identical.

    Abstract translation: 本发明涉及一种用于制作安全秘密数量的方法和系统，其包含在电子设备中，并且至少部分地用于执行预定数目（N）的连续迭代的输入数据的至少一部分的加密算法中， 公共函数并产生输出数据的至少一部分，其包括：在第一数目（X）的迭代之后存储（14）中间结果; 向输出数据应用与加密的函数相反的函数，用于对应于迭代总数与第一数目之间的差的迭代次数（N-X）; 将所述中间结果与所述反函数的迭代结果进行比较（18）; 并且只有在两个结果相同的情况下才验证加密。

    LOW-NOISE LOAD PUMP FOR PHASE-LOCKING LOOP
    195.
    发明申请
    LOW-NOISE LOAD PUMP FOR PHASE-LOCKING LOOP 审中-公开
    低噪声负载泵用于相位锁定环

    公开(公告)号：WO02054597A3

    公开(公告)日：2003-03-13

    申请号：PCT/FR0104224

    申请日：2001-12-28

    Applicant: ST MICROELECTRONICS SA ,  RAMET SERGE ,  RIEUBON SEBASTIEN

    Inventor： RAMET SERGE ,  RIEUBON SEBASTIEN

    IPC: H03L7/093 ,  H03L7/089 ,  H03L7/18

    CPC classification number: H03L7/0896 ,  H03L7/18

    Abstract: The invention concerns a load pump for phase-locking loop comprising a first current source (14), a second current source (16), several switches (M1, M2, M3, M4) adapted to communicate the first and/or the second current source with the load pump output (OUT). The second current source is driven by control means (18) adapted to store a physical quantity corresponding to the value of the current (l1) supplied by the first current source (14), so that the value of current (l2) supplied by the second current source is substantially equal to the value of current (l1) supplied by the first current source.

    Abstract translation: 本发明涉及一种用于锁相环的负载泵，包括第一电流源（14），第二电流源（16），适于传送第一和/或第二电流的多个开关（M1，M2，M3，M4） 源与负载泵输出（OUT）。 第二电流源由适于存储对应于由第一电流源（14）提供的电流（l1）的值的物理量的控制装置（18）驱动，使得由第一电流源（14）提供的电流（l2） 第二电流源基本上等于由第一电流源提供的电流（l1）的值。

    AUXILIARY SWITCHING CIRCUIT FOR A CHOPPING CONVERTER
    198.
    发明申请
    AUXILIARY SWITCHING CIRCUIT FOR A CHOPPING CONVERTER 审中-公开
    辅助转换器的辅助开关电路

    公开(公告)号：WO02073783A2

    公开(公告)日：2002-09-19

    申请号：PCT/FR0200842

    申请日：2002-03-08

    Applicant: ST MICROELECTRONICS SA ,  PERON BENOIT

    Inventor： PERON BENOIT

    IPC: H02M3/155

    CPC classification number: H02M3/155

    Abstract: The invention relates to an auxiliary switching circuit (10) for a chopping converter comprising a first inductive element (L0) for serial energy storage with a free-wheel diode (DL) and a switch (K), in addition to a second inductive element (L) for di/dt control when the switch is closed, the auxialiary switching circuit comprising a magnetic circuit (11) whereby a main winding thereof is formed at least partially by the first inductive element (L0), also comprising means (L1, D1, L2, D2) for discharging the second inductive element when the switch is opened or closed, and means (L2, D2) for transferring the energy corresponding to the closure vis a vis said main winding.

    Abstract translation: 本发明涉及一种用于斩波转换器的辅助开关电路（10），该辅助开关电路除了第二电感元件（L）以外还包括用于具有续流二极管（DL）和开关（K）的串联储能的第一电感元件（L0） （L）用于开关闭合时的di / dt控制，所述辅助开关电路包括磁路（11），由此其主绕组至少部分地由第一电感元件（L0）形成，还包括装置（L1， （L2，D2），用于当所述开关打开或闭合时释放所述第二感应元件，以及用于将对应于所述闭合件的能量传递给所述主绕组的装置（L2，D2）。

    METHOD FOR PRODUCING A CAPACITOR
    199.
    发明申请
    METHOD FOR PRODUCING A CAPACITOR 审中-公开
    生产电容器的方法

    公开(公告)号：WO2014016147A3

    公开(公告)日：2014-03-20

    申请号：PCT/EP2013064863

    申请日：2013-07-12

    Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

    Inventor： LAMY YANN ,  GUILLER OLIVIER ,  JOBLOT SYLVAIN

    IPC: H01G4/33 ,  H01G4/38 ,  H01L49/02

    CPC classification number: H01G4/306 ,  H01G4/33 ,  H01G4/38 ,  H01L28/87 ,  H01L28/91 ,  H05K1/181

    Abstract: The invention concerns a method for producing a capacitor, comprising the forming of a capacitor stack in one portion of a substrate (112), said method comprising: the forming of a cavity (165) along the thickness of the portion of the substrate (112) from an upper face of said substrate (112), the depositing of a plurality of layers contributing to the capacitor stack onto the wall of the cavity (165) and onto the surface of the upper face, and a removal of matter from the layers until the surface of the upper face is reached, characterised in that the formation of the cavity (165) comprises the formation of at least one trench (164) and, associated with each trench (164), of at least one box (163), said at least one trench (164) comprising a trench outlet that opens into the box (163), said box (163) comprising a box outlet that opens at the surface of the upper face, the box outlet being shaped so as to be larger than the trench outlet.

    Abstract translation: 本发明涉及一种用于制造电容器的方法，该方法包括在衬底（112）的一部分中形成电容器叠层，所述方法包括：沿衬底（112）部分的厚度形成空腔（165） ）与所述衬底（112）的上表面接触，将有助于电容器堆叠的多个层沉积到空腔（165）的壁上并沉积到上表面的表面上，以及从层 直至到达上表面的表面，其特征在于，空腔（165）的形成包括形成至少一个箱（163）的至少一个沟槽（164）并且与每个沟槽（164）相关联， ，所述至少一个沟槽（164）包括通向所述箱（163）的沟槽出口，所述箱（163）包括在所述上表面的表面处开口的箱出口，所述箱出口成形为 大于沟槽出口。

Patent Agency Ranking