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    디지털 전송 시스템들과 함께 사용하기 위한 소형 전자기커플러
    192.
    发明授权
    디지털 전송 시스템들과 함께 사용하기 위한 소형 전자기커플러 失效
    紧凑型电磁耦合器，用于数字传输系统

    公开(公告)号：KR100750038B1

    公开(公告)日：2007-08-16

    申请号：KR1020057022967

    申请日：2004-05-20

    Applicant: 인텔 코포레이션

    Inventor： 벤함,존 ,  크릿크로우,존 ,  리앙,타오

    IPC: G06F13/40 ,  H03K19/0175

    CPC classification number: G06F13/4086 ,  H01P5/185 ,  H05K1/0239 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/10189

    Abstract: 디지털 전송 시스템과 함께 사용하기 위한 소형 전자기 커플러가 기술된다. 일 실시예에서, 이 장치는 기하학적 구조를 갖는 부분을 포함하는 제1 전송 구조를 포함한다. 기하학적 구조를 갖고, 제1 전송 구조와 전자기 커플러를 형성하기 위해 기하학적 구조를 갖는 제1 전송 구조의 상기 부분 근처에 배치되는 제2 전송 구조와 표준 카드 커넥터의 풋프린트(footprint) 내의 배치를 가능하게 하는 전자기 커플러의 기하학적 구조가 제공된다. 소형 전자기 커플러는 제1 전송 구조를 따라 전송된 신호의 타이밍 및 논리적 상태의 재구성을 가능하게 하도록 형성된다.
    기하학적 구조, 마이크로스트립, 전자기 커플러, 크로스토크, 재구성

    인쇄 회로 기판을 위한 우선적 접지 및 바이어 진출 구조물
    193.
    发明公开
    인쇄 회로 기판을 위한 우선적 접지 및 바이어 진출 구조물 失效
    优选地面和通过印刷电路板的出口结构

    公开(公告)号：KR1020060118605A

    公开(公告)日：2006-11-23

    申请号：KR1020067018637

    申请日：2005-02-14

    Applicant: 몰렉스 엘엘씨

    Inventor： 레그니어켄트이. ,  브런커데이비드엘. ,  오그부오키리마틴유.

    IPC: H05K1/09

    CPC classification number: H05K1/0245 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10189 ,  H01L2924/00

    Abstract: A circuit board design is disclosed that is useful in high speed differential signal applications uses either a via arrangement or a circuit trace exit structure. In the via arrangement, sets of differential signal pair vias and an associated ground are arranged adjacent to each other in a repeating pattern. The differential signal vias of each pair are spaced closer to their associated ground via than the spacing between the adjacent differential signal pair associated ground so that differential signal vias exhibit a preference for electrically coupling to their associated ground vias. The circuit trace exit structure involves the exit portions of the circuit traces of the differential signal vias to follow a path where the traces then meet with and join to the transmission line portions of the conductive traces.

    Abstract translation: 公开了一种在高速差分信号应用中使用电路布置或电路走线出口结构的电路板设计。 在通孔布置中，差分信号对通孔和相关接地的组以重复图案彼此相邻布置。 每对的差分信号通孔比相邻的差分信号对相关联的接地之间的间隔更靠近其相关联的接地间隔，使得差分信号通孔表现出对它们相关的接地通孔的电耦合的偏好。 电路走线出口结构涉及差分信号通孔的电路迹线的出口部分，以跟随路径，其中迹线然后与导电迹线的传输线部分相接合并连接到导体迹线的传输线部分。

    고주파 잡음을 감소시키는 데이터 버스 구조를 가지는반도체 메모리 장치
    194.
    发明授权
    고주파 잡음을 감소시키는 데이터 버스 구조를 가지는반도체 메모리 장치 失效
    고주파잡음을감소키시키는데이터버스구조를가지는반도체메모리장치

    公开(公告)号：KR100450677B1

    公开(公告)日：2004-10-01

    申请号：KR1020020031410

    申请日：2002-06-04

    Applicant: 삼성전자주식회사

    Inventor： 박면주 ,  이재준

    IPC: G06F13/40

    CPC classification number: H05K1/0216 ,  G11C7/1006 ,  H05K1/0237 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09727 ,  H05K2201/09781

    Abstract: A semiconductor memory device includes memory modules which have memories and a data bus which transfers data to the memory modules, in which the data bus comprises a low frequency band data pass unit which removes the high frequency component of the data and sends the data to the memory modules. The low frequency band data pass unit comprises a plurality of stubs which are connected to the data bus in parallel and are formed as printed circuit board (PCB) patterns. The low frequency band data pass unit comprises a plurality of plates that are connected to the data bus in parallel and are formed as PCB patterns. The low frequency band data pass unit has a shape in which parts having a wide width and parts having a narrow width are alternately connected. Therefore, without adding a separate passive device, the semiconductor memory device reduces the high frequency noise of data transferred through a data bus such that the voltage margin of the data improves, the cost for passive devices such as capacitors, is reduced, and the process for attaching the passive devices is simplified.

    Abstract translation: 半导体存储器件包括具有存储器和将数据传输到存储器模块的数据总线的存储器模块，其中数据总线包括低频带数据传递单元，该单元移除数据的高频分量并将数据发送到 内存模块。 低频带数据传递单元包括并联连接到数据总线并形成为印刷电路板（PCB）图案的多个短截线。 低频带数据传递单元包括并联连接到数据总线并形成为PCB图案的多个板。 低频带数据传递单元具有宽度宽的部分和宽度窄的部分交替连接的形状。 因此，在不添加单独的无源器件的情况下，半导体存储器件减少了通过数据总线传输的数据的高频噪声，使得数据的电压裕度提高，无源器件例如电容器的成本降低，并且工艺 用于连接无源器件被简化。

    고주파 잡음을 감소시키는 데이터 버스 구조를 가지는반도체 메모리 장치
    195.
    发明公开
    고주파 잡음을 감소시키는 데이터 버스 구조를 가지는반도체 메모리 장치 失效
    具有数据总线结构的半导体存储器件降低高频噪声

    公开(公告)号：KR1020030094569A

    公开(公告)日：2003-12-18

    申请号：KR1020020031410

    申请日：2002-06-04

    Applicant: 삼성전자주식회사

    Inventor： 박면주 ,  이재준

    IPC: G06F13/40

    CPC classification number: H05K1/0216 ,  G11C7/1006 ,  H05K1/0237 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09727 ,  H05K2201/09781

    Abstract: PURPOSE: A semiconductor memory device having a data bus architecture reducing high frequency noise is provided to remove the high frequency noise and to transfer low frequency data by using a PCB(Printed Circuit Board) pattern. CONSTITUTION: The semiconductor memory device(200) includes memory modules(MM1-MM4) and a data bus(DABUS) transferring the data applied to the memory modules. The data bus includes a low band data path part(220) removing a high frequency component of the data and transferring it to the memory modules. The low band data path part includes the stubs serially connected to the data bus and formed by the PCB pattern. An end terminal not connected to the data bus of the stubs is opened. The low band data path part includes the plates serially connected to the data bus and formed by the PCB pattern. The plates are connected to the data bus by a short circuit made of the PCB pattern. The low band data path part has a shape that the data bus has a wide and a narrow part alternately.

    Abstract translation: 目的：提供具有降低高频噪声的数据总线结构的半导体存储器件，以消除高频噪声并通过使用PCB（印刷电路板）图案传送低频数据。 构成：半导体存储器件（200）包括传送应用于存储器模块的数据的存储器模块（MM1-MM4）和数据总线（DABUS）。 数据总线包括去除数据的高频分量并将其传送到存储器模块的低频带数据路径部分（220）。 低频数据路径部分包括串行连接到数据总线并由PCB图形形成的短截线。 未连接到存根的数据总线的终端被打开。 低频数据路径部分包括串行连接到数据总线并由PCB图案形成的板。 板通过PCB图案的短路连接到数据总线。 低频数据路径部分具有数据总线交替具有宽和窄部分的形状。

    반도체 집적회로 및 전자회로
    196.
    发明公开
    반도체 집적회로 및 전자회로 失效
    半导体集成电路和电子电路

    公开(公告)号：KR1020010082537A

    公开(公告)日：2001-08-30

    申请号：KR1020000063379

    申请日：2000-10-27

    Applicant: 엘피다 메모리 가부시키가이샤

    Inventor： 후나바세이지 ,  니시오요지

    IPC: G11C7/10

    CPC classification number: G11C7/22 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  H05K1/0248 ,  H05K1/0268 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09781

    Abstract: PURPOSE: To suppress ringings, occurring on a transmission line in conformity with the situation of a packaged system even when high-speed operation with small signal amplitude. CONSTITUTION: Dummy wiring 25 is provided simulating actual wiring 26, that connects semiconductor integrated circuits 2, 6 on a circuit board. The integrated circuits have a data output circuit 28 with a variable slew rate and a circuit 29 for measuring signal delay time from a signal send-out point to a signal reflection point (characteristic impedance mismatch point) by using the dummy wiring 25. Signal transition time of the output circuit is determined, by using the delay time obtained by the measuring circuit. The transition time is at least twice the delay time, which extends from the send-out point to the nearest branch of the wiring. This enables transmission of signals with mitigated reflection by the nearest reflection point.

    Abstract translation: 目的：抑制振铃，即使在信号幅度较小的高速运行时也符合封装系统的情况，传输线上发生振铃。 实施例：虚拟接线25被模拟实际布线26，其连接电路板上的半导体集成电路2,6。 集成电路具有可变转换速率的数据输出电路28和用于通过使用虚拟布线25测量从信号发出点到信号反射点（特征阻抗失配点）的信号延迟时间的电路29。信号转换 通过使用由测量电路获得的延迟时间来确定输出电路的时间。 转换时间至少是延迟时间的两倍，延迟时间从发送点延伸到布线最近的分支。 这使得能够通过最近的反射点传输具有减轻反射的信号。

    一种连接器及电子设备
    197.
    发明申请
    一种连接器及电子设备 审中-公开

    公开(公告)号：WO2014071722A1

    公开(公告)日：2014-05-15

    申请号：PCT/CN2013/074270

    申请日：2013-04-16

    Applicant: 华为技术有限公司

    Inventor： 肖聪图 ,  赵志刚

    IPC: H01R13/66

    CPC classification number: H05K1/14 ,  H01R12/724 ,  H01R13/6625 ,  H01R13/665 ,  H05K3/366 ,  H05K2201/044

    Abstract: 一种连接器以及包括连接器的电子设备。连接器（30）包括：第一接口、第二接口以及信号增强电路（23），第一接口、第二接口中至少一个接口包括电源触头（207），电源触头用于为信号增强电路供电；外壳，信号增强电路设置于外壳内部并串接于第一接口和第二接口之间，信号增强电路对第一接口接收到的差分信号进行信号放大处理并通过第二接口输出，第一接口、第二接口设置于外壳外部的不同表面上。连接器及其电子设备可在高传输数据速率下控制信号衰减，同时又不增加电路板的体积。

    信号传输装置及电子设备
    198.
    发明申请
    信号传输装置及电子设备 审中-公开

    公开(公告)号：WO2014063350A1

    公开(公告)日：2014-05-01

    申请号：PCT/CN2012/083580

    申请日：2012-10-26

    Applicant: 华为技术有限公司

    Inventor： 刘金水 ,  邓治高

    IPC: H01R12/79 ,  H01R13/62

    CPC classification number: H05K1/115 ,  H05K3/366 ,  H05K2201/044 ,  H05K2201/09609 ,  H05K2201/10189 ,  H05K2201/10545

    Abstract: 本发明提供一种信号传输装置和电子设备，其中，信号传输装置包括：背板和至少两组连接器组合；其中每一组连接器组合包括：位于所述背板第一面的至少一个第一连接器，和位于所述背板第二面的至少一个第二连接器，所述每一组连接器组合的方向为：所述每一组连接器组合中的一个第二连接器的重合区域朝向该第二连接器的非重合区域的方向；所述至少一个第一连接器在所述背板的第一面形成队列结构，若所述至少两组连接器组合中的第一组连接器组合与第二组连接器组合为相邻的连接器组合，则所述第一组连接器组合的方向与所述第二组连接器组合的方向相反。上述信号传输装置解决了现有技术中的半正交架构的信号传输装置中的问题。

    SERIAL LINK INTERCONNECTION ARRANGEMENT FOR BACKPLANE WITH EMBEDDED WAVEGUIDE
    199.
    发明申请
    SERIAL LINK INTERCONNECTION ARRANGEMENT FOR BACKPLANE WITH EMBEDDED WAVEGUIDE 审中-公开
    带有嵌入式波导的背板的串行链路互连布置

    公开(公告)号：WO2012159933A2

    公开(公告)日：2012-11-29

    申请号：PCT/EP2012/058992

    申请日：2012-05-15

    Applicant: ALCATEL LUCENT ,  HOOGHE, Koen

    Inventor： HOOGHE, Koen

    IPC: H05K1/14 ,  H05K1/02 ,  G06F13/40 ,  H05K7/14

    CPC classification number: H05K1/14 ,  H01P5/103 ,  H05K1/0243 ,  H05K1/141 ,  H05K7/1459 ,  H05K2201/0311 ,  H05K2201/044 ,  H05K2201/10189

    Abstract: A serial link interconnection arrangement for interconnecting a first printed circuit board (BoardA) with a second printed circuit board (BoardB), both boards being inserted in a backplane of a telecommunication system. The arrangement comprises a waveguide embedded in the backplane. A first end (WavA) of the waveguide is coupled to the first board (BoardA) via a first connection system (ConA), whilst the second end (WavB) of the waveguide is coupled to the second board (BoardB) via a second connection system (ConB). Each of the connection systems (ConA; ConB) comprises a transceiver (IntA; IntB) adapted to convert a parallel signal received from the printed circuit board (BoardA; BoardB) into a serial stream transmitted to an end (WavA; WavB) of the waveguide via an antenna (AntA; AntB), and vice-versa.

    Abstract translation: 一种用于将第一印刷电路板（BoardA）与第二印刷电路板（BoardB）互连的串行链路互连装置，两个板插入电信系统的背板中。 该布置包括嵌入背板中的波导。 波导的第一端（WavA）通过第一连接系统（ConA）耦合到第一板（BoardA），而波导的第二端（WavB）通过第二连接耦合到第二板（BoardB） 系统（ConB）。 每个连接系统（ConA; ConB）包括适于将从印刷电路板（BoardA; BoardB）接收的并行信号转换成传输到端部（WavA; WavB）的串行流的收发器（IntA; IntB） 波导通过天线（AntA; AntB），反之亦然。

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