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    A CIRCUIT, CORRESPONDING SYSTEM, VEHICLE AND METHOD OF OPERATION
    202.
    发明公开
    A CIRCUIT, CORRESPONDING SYSTEM, VEHICLE AND METHOD OF OPERATION 审中-公开

    公开(公告)号：EP3920410A1

    公开(公告)日：2021-12-08

    申请号：EP21305639.3

    申请日：2021-05-17

    Applicant: STMicroelectronics (ALPS) SAS ,  STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

    Inventor： OCCHIPINTI, Aldo ,  ROUSSEL, Christophe ,  BURKHARDT, Fritz ,  TESTONI, Ignazio

    IPC: H02P29/024 ,  H02P29/028

    Abstract: A driver circuit (30) comprises a power supply pin (300) configured to receive a power supply voltage ( V s ), and a set of control pins (302a, 302b, 304a, 304b) configured to provide a set of control signals for controlling the switching activity of a set of switches of an h-bridge circuit. The set of switches of the h-bridge circuit comprises a pair of high-side switches and a pair of low-side switches.
    The driver circuit (30) comprises control circuitry (36) coupled (32a, 32b, 34a, 34b) to the control pins (302a, 302b, 304a, 304b) and configured to generate the control signals, and sensing circuitry (38, 360) coupled to the power supply pin (300) and configured to generate a detection signal indicative of said power supply voltage ( V s ) exceeding a threshold value.
    The control circuitry (36) is sensitive to the detection signal and is configured to generate said control signals to activate one of said pair of high-side switches and said pair of low-side switches and deactivate the other of said pair of high-side switches and said pair of low-side switches as a result of said detection signal being indicative of said power supply voltage ( V s ) exceeding said threshold value.

    A PROCESSING SYSTEM COMPRISING A QUEUED SERIAL PERIPHERAL INTERFACE, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
    203.
    发明公开
    A PROCESSING SYSTEM COMPRISING A QUEUED SERIAL PERIPHERAL INTERFACE, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD 审中-公开

    公开(公告)号：EP3885924A1

    公开(公告)日：2021-09-29

    申请号：EP21162262.6

    申请日：2021-03-12

    Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

    Inventor： NANDLINGER, Mr. Rolf ,  OLEXA, Mr. Radek

    IPC: G06F13/40

    Abstract: A processing system (10a) comprising a queued Serial Peripheral Interface, SPI, circuit (30a) is described. The SPI circuit (30a) comprises a hardware SPI communication interface (36), an arbiter (34) and a plurality of interface circuits (32 0 ..32 n ). Specifically, each interface circuit (32 0 ..32 n ) comprises a transmission FIFO memory (320), a reception FIFO memory (322) and an interface control circuit (324). The interface control circuit (324) is configured to receive one or more first data packets from a digital processing circuit (102) and store the received one or more first data packets to the transmission FIFO memory (320). Next, the interface control circuit (324) sequentially reads the one or more first data packets from the transmission FIFO memory (320), extracts from the one or more first data packets at least one transmission data word (DATA), and provides the at least one extracted transmission data word (DATA) to the arbiter (34). In turn, interface control circuit (324) receives from the arbiter (34) a reception data word (RXDATA) and stores one or more second data packets to the reception FIFO memory (322), the one or more second data packets comprising the received reception data word (RXDATA). Finally, the interface control circuit (324) sequentially reads the one or more second data packets from the reception FIFO memory (322) and transmits the one or more second data packets to the digital processing circuit (102).

    AN ELECTRONIC DEVICE, A CORRESPONDING COMMUNICATION SYSTEM AND A VEHICLE COMPRISING THE SYSTEM
    204.
    发明公开
    AN ELECTRONIC DEVICE, A CORRESPONDING COMMUNICATION SYSTEM AND A VEHICLE COMPRISING THE SYSTEM 审中-公开

    公开(公告)号：EP3879730A1

    公开(公告)日：2021-09-15

    申请号：EP21158711.8

    申请日：2021-02-23

    Applicant: STMicroelectronics Application GmbH

    Inventor： RENNIG, Mr. Fred

    IPC: H04L1/00 ,  H04L12/40 ,  H04L12/403 ,  G06F11/07 ,  B60R16/023

    Abstract: An electronic device is configured for coupling to a communication bus to receive therefrom frames encoded according to a communication protocol. The electronic device comprises a check circuit sensitive to said frames and configured to perform a check (203, 204, 205) as to whether a received frame is encoded according to said communication protocol and is addressed to the electronic device. The electronic device comprises a frame counter circuit configured to count frames received during a monitoring time interval by increasing a frame count value as a result of a positive outcome of said check. The electronic device comprises a comparator circuit configured to set a status bit to a first value indicative of a first operating status of the electronic device as a result of the frame count value being equal (208) to a first threshold value, and to a second value indicative of a second operating status of the electronic device as a result of the frame count value being equal (210) to a second threshold value. The electronic device comprises a controller circuit configured to transmit (212a) over the communication bus a frame comprising the status bit, and configured to reset (214) the frame count value at the end of the monitoring time interval.
    The frame counter circuit comprises a modular arithmetic counter circuit having a certain bit depth. The frame count value is constrained to a modulus value of the modular arithmetic counter circuit.

    PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
    206.
    发明公开
    PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD 审中-公开

    公开(公告)号：EP3657345A1

    公开(公告)日：2020-05-27

    申请号：EP19208829.2

    申请日：2019-11-13

    Applicant: STMicroelectronics Application GmbH

    Inventor： COLOMBO, Mr. Roberto

    IPC: G06F15/177 ,  G06F9/445 ,  G06F11/10

    Abstract: A processing system (10a) is described. The processing system comprises a plurality of configuration data client circuits (112), a hardware circuit (110) configured to change operation as a function of configuration data (CD) stored by the configuration data client circuits (112), a non-volatile memory (104) comprising the configuration data (CD) for the hardware circuit (110), and a hardware configuration circuit (108a) configured to read the configuration data (CD) from the non-volatile memory (104) and transmit the configuration data (CD) to the configuration data client circuits (112) . The configuration data (CD) are stored in the non-volatile memory (104) in the form of data packets (DCF1..DCFn) comprising an address (ADR) and respective configuration data (CD).
    Specifically, the hardware configuration circuit (108a) is configured to sequentially read (1080) the data packets (DCF1..DCFn) from the non-volatile memory (104), select a target configuration data client circuit (112), and transmit (1082) via a first data signal (DATA) the configuration data (CD) included in the data packet (DCFi) to a respective target configuration data client circuit (112). Moreover, the hardware configuration circuit (108a) is configured to receiving via a second data signal (DATA', ADR') the configuration data (CD) stored by the target configuration data client circuit (112) and the respective address associated with the target configuration data client circuit (112). Thus, the hardware configuration circuit (108a) may comparing (1090) the configuration data and address received from the target configuration data client circuit (112) with the content of the data packets (DCF1..DCFn) read from the non-volatile memory (104), and possibly generate an error signal.

    PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT AND METHOD
    208.
    发明公开
    PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT AND METHOD 审中-公开

    公开(公告)号：EP3534262A1

    公开(公告)日：2019-09-04

    申请号：EP19159273.2

    申请日：2019-02-26

    Applicant: STMicroelectronics Application GmbH

    Inventor： COLOMBO, Mr. Roberto

    IPC: G06F11/10

    Abstract: A processing system is described. The processing system comprises a processing unit, such as a microprocessor, arranged to be connected to a memory with error detection and/or correction. Specifically, the processing unit generates at least one read request for reading data from the memory, the read request comprising an address signal ( ADR ) identifying the address of a given memory area in the memory. The processing system comprises moreover an error handling circuit (108) arranged to be connected to the memory for receiving an error signal ( ERR ) , wherein the error signal ( ERR ) contains an error code indicating whether the data read from the memory contain errors (UC). Specifically, the error handling circuit (108) comprises a hardware circuit (1084, 1086) configured to set a first error signal ( ERR' 1 ) to the error code of the error signal ( ERR ) when the address indicated by the address signal ( ADR ) belongs to a first address range ( RL 1 , RH 1 ) and to set a second error signal ( ERR' n ) to the error code of the error signal ( ERR ) when the address indicated by the address signal ( ADR ) belongs to a second address range ( RL n , RH n ).

    Battery comprising circuitry for charge and discharge control, and method of operating a battery
    209.
    发明公开
    Battery comprising circuitry for charge and discharge control, and method of operating a battery 审中-公开
    具有用于充电和放电控制中，和方法的电路装置的电池用于操作电池

    公开(公告)号：EP2445081A3

    公开(公告)日：2015-08-26

    申请号：EP11182601.2

    申请日：2011-09-23

    Applicant: STMicroelectronics Application GmbH

    Inventor： Schwartz, Reiner

    IPC: H02J7/00

    CPC classification number: H02J7/0026 ,  H02J7/0016 ,  H02J2007/0037 ,  H02J2007/004 ,  Y02T10/7055

    Abstract: A battery and a method of operating a battery are provided. The battery comprises at least one battery module. Each battery module comprises a plurality of submodules electrically connected in series. Each submodule comprises a first and a second submodule terminal and at least one cell. At least one submodule in each battery module is a switchable submodule comprising a submodule switching circuit. The submodule switching circuit is switchable between a first state and a second state. The submodule switching circuit electrically connects the at least one cell of the switchable submodule between the first and the second submodule terminal of the switchable submodule when the submodule switching circuit is in the first state. The submodule switching circuit provides an electrical bypass connection between the first and the second submodule terminal of the switchable submodule and the at least one cell of the switchable submodule is electrically disconnected from at least one of the first and the second submodule terminal when the switching circuit is in the second state. The battery further comprises a control unit for operating the switching circuit in the at least one switchable submodule of each module.

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