公开(公告)号：EP3432190B1

公开(公告)日：2020-09-23

申请号：EP18182223.0

申请日：2018-07-06

Applicant: STMicroelectronics Application GmbH

Inventor： COLOMBO, Mr. Roberto

IPC: G06F21/71 ,  G06F21/44

公开(公告)号：EP3534261A1

公开(公告)日：2019-09-04

申请号：EP19159293.0

申请日：2019-02-26

Applicant: STMicroelectronics Application GmbH

Inventor： COLOMBO, Mr. Roberto

IPC: G06F11/07 ,  G06F11/10

Abstract: A processing system (10a) is described. The processing system (10a) comprises a plurality of circuits (102, 104, 106) configured to generate a plurality of error signals ( ERR ) and a plurality of error pads (EP). A fault collection circuit (108) is configured to receive at input the error signals ( ERR ) and generate a respective combined error signal ( ET ) for each of said error pads (EP). Specifically, the fault collection circuit (108) comprises a combinational logic circuit configured to generate the combined error signal ( ET ) by selectively routing the error signals ( ERR ) to the error pads (EP) as a function of a set of configuring bits.

公开(公告)号：EP3534261B1

公开(公告)日：2020-11-04

申请号：EP19159293.0

申请日：2019-02-26

Applicant: STMicroelectronics Application GmbH

Inventor： COLOMBO, Mr. Roberto

IPC: G06F11/07 ,  G06F11/10

公开(公告)号：EP3657345A1

公开(公告)日：2020-05-27

申请号：EP19208829.2

申请日：2019-11-13

Applicant: STMicroelectronics Application GmbH

Inventor： COLOMBO, Mr. Roberto

IPC: G06F15/177 ,  G06F9/445 ,  G06F11/10

Abstract: A processing system (10a) is described. The processing system comprises a plurality of configuration data client circuits (112), a hardware circuit (110) configured to change operation as a function of configuration data (CD) stored by the configuration data client circuits (112), a non-volatile memory (104) comprising the configuration data (CD) for the hardware circuit (110), and a hardware configuration circuit (108a) configured to read the configuration data (CD) from the non-volatile memory (104) and transmit the configuration data (CD) to the configuration data client circuits (112) . The configuration data (CD) are stored in the non-volatile memory (104) in the form of data packets (DCF1..DCFn) comprising an address (ADR) and respective configuration data (CD).
Specifically, the hardware configuration circuit (108a) is configured to sequentially read (1080) the data packets (DCF1..DCFn) from the non-volatile memory (104), select a target configuration data client circuit (112), and transmit (1082) via a first data signal (DATA) the configuration data (CD) included in the data packet (DCFi) to a respective target configuration data client circuit (112). Moreover, the hardware configuration circuit (108a) is configured to receiving via a second data signal (DATA', ADR') the configuration data (CD) stored by the target configuration data client circuit (112) and the respective address associated with the target configuration data client circuit (112). Thus, the hardware configuration circuit (108a) may comparing (1090) the configuration data and address received from the target configuration data client circuit (112) with the content of the data packets (DCF1..DCFn) read from the non-volatile memory (104), and possibly generate an error signal.

公开(公告)号：EP3534262A1

公开(公告)日：2019-09-04

申请号：EP19159273.2

申请日：2019-02-26

Applicant: STMicroelectronics Application GmbH

Inventor： COLOMBO, Mr. Roberto

IPC: G06F11/10

Abstract: A processing system is described. The processing system comprises a processing unit, such as a microprocessor, arranged to be connected to a memory with error detection and/or correction. Specifically, the processing unit generates at least one read request for reading data from the memory, the read request comprising an address signal ( ADR ) identifying the address of a given memory area in the memory. The processing system comprises moreover an error handling circuit (108) arranged to be connected to the memory for receiving an error signal ( ERR ) , wherein the error signal ( ERR ) contains an error code indicating whether the data read from the memory contain errors (UC). Specifically, the error handling circuit (108) comprises a hardware circuit (1084, 1086) configured to set a first error signal ( ERR' 1 ) to the error code of the error signal ( ERR ) when the address indicated by the address signal ( ADR ) belongs to a first address range ( RL 1 , RH 1 ) and to set a second error signal ( ERR' n ) to the error code of the error signal ( ERR ) when the address indicated by the address signal ( ADR ) belongs to a second address range ( RL n , RH n ).

公开(公告)号：EP3534262B1

公开(公告)日：2020-11-04

申请号：EP19159273.2

申请日：2019-02-26

Applicant: STMicroelectronics Application GmbH

Inventor： COLOMBO, Mr. Roberto

IPC: G06F11/10

公开(公告)号：EP3531289B1

公开(公告)日：2020-11-04

申请号：EP19156613.2

申请日：2019-02-12

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

Inventor： COLOMBO, Mr. Roberto ,  RANJAN, Mr. Om

IPC: G06F11/10

公开(公告)号：EP3514685B1

公开(公告)日：2020-10-07

申请号：EP19150934.8

申请日：2019-01-09

Applicant: STMicroelectronics Application GmbH

Inventor： COLOMBO, Mr. Roberto

IPC: G06F9/445 ,  G06F9/4401

公开(公告)号：EP3531289A1

公开(公告)日：2019-08-28

申请号：EP19156613.2

申请日：2019-02-12

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

Inventor： COLOMBO, Mr. Roberto ,  RANJAN, Mr. Om

IPC: G06F11/10

Abstract: A processing system (10a) is described. The processing system (10a) comprises configuration data clients (112), wherein with each configuration data client (112) is associated a respective address (ADR). The configuration data (CD) for the plurality of configuration data clients (112) are store in a non-volatile memory (104), wherein the configuration data (CD) are stored in the form of data packets (DCF_x, DCF_y, DCF_z) comprising an attribute field identifying the address (ADR) of one of the configuration data clients (112) and the respective configuration data. A hardware configuration module (108) sequentially reads (1080) the data packets from the non-volatile memory (104) and transmit the configuration data (DATA) read to the respective configuration data client (112).
Specifically, the non-volatile memory (104) comprises first signature data (HASH), wherein the hardware configuration module (108) reads also the first signature data (HASH). Moreover, the processing system (10a) comprises a signature calculation circuit (130) configured to calculate second signature data (HASH') as a function of the respective configuration data (DATA) transmitted to the configuration data clients (112) and/or stored in the configuration data clients (112). Accordingly, a signature verification circuit (132) may compare the first signature data (HASH) with the second signature data (HASH') and possibly generate an error signal (ERR).

公开(公告)号：EP3514685A1

公开(公告)日：2019-07-24

申请号：EP19150934.8

申请日：2019-01-09

Applicant: STMicroelectronics Application GmbH

Inventor： COLOMBO, Mr. Roberto

IPC: G06F9/445

Abstract: The present disclosure relates to a processing system. The processing system comprises a plurality of configuration data clients (112), wherein each configuration data client (112) is configured to receive configuration data (CD) addressed to a respective address and store the configuration data (CD) received in a respective register (118). The processing system comprises also at least one hardware block configured to change operation as a function of the configuration data (CD) stored in the registers (118) of the configuration data clients (112), and a non-volatile memory (104) configured to store the configuration data (CD) for the plurality of configuration data clients (112). Specifically, the configuration data are stored in the form of data packets. A hardware configuration module (108) sequentially reads the data packets from the non-volatile memory (104) and transmit the respective configuration data read from the non-volatile memory (104) to the respective configuration data client (112).
Specifically, at least one of the configuration data clients (112) is configured to receive a first set of configuration data addressed to the respective address and store (1024) the first set of configuration data received in the respective register (118). Moreover, the configuration data client (112) may receive a second set of configuration data addressed to the respective address. In response to the second set of configuration data, the configuration data client (112) verifies (1022) whether further configuration data may be written to the respective register as a function of at least one type identification signal (TI).