中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

204 records (took 0.029 seconds)

    BIAS VOLTAGE DISTRIBUTION SYSTEM
    201.
    发明公开
    BIAS VOLTAGE DISTRIBUTION SYSTEM 失效
    偏压配电系统

    公开(公告)号：EP0698235A1

    公开(公告)日：1996-02-28

    申请号：EP94916588.0

    申请日：1994-04-28

    Applicant: MicroUnity Systems Engineering, Inc.

    Inventor： HERNDON, William, H.

    IPC: G05F3 ,  H03K19

    CPC classification number: G05F3/24

    Abstract: The present invention describes a bias potential distribution system which provides bias potentials to MOS devices while ensuring the devices' operating conditions remain constant over temperature, process, and power supply fluctuations. Further, bias potentials are generated at one main location within the logic circuit and then distributed throughout the logic circuit to all of the MOS devices or to bias voltage conversion circuits.

    Abstract translation: 本发明描述了一种偏压电势分布系统，其向MOS器件提供偏压电势，同时确保器件的工作条件在温度，工艺和电源波动中保持恒定。 此外，在逻辑电路内的一个主要位置处产生偏置电位，然后将其分布在整个逻辑电路中的所有MOS器件或偏置电压转换电路。

    BICMOS ECL-TO-CMOS LEVEL TRANSLATOR AND BUFFER
    202.
    发明公开
    BICMOS ECL-TO-CMOS LEVEL TRANSLATOR AND BUFFER 失效
    BiCMOS工艺ECL设为CMOS电平转换器和缓冲电路。

    公开(公告)号：EP0655177A1

    公开(公告)日：1995-05-31

    申请号：EP93914239.0

    申请日：1993-05-28

    Applicant: MicroUnity Systems Engineering, Inc.

    Inventor： WONG, Ban, Pak

    IPC: H03K19

    CPC classification number: H03K19/018521 ,  H03K19/00361 ,  H03K19/0136 ,  H03K19/017518

    Abstract: An ECL-to-CMOS level translator and BiCMOS buffer are described. The current supplied from the first input PMOS transistor (P1) is the input current to a current mirror comprising the first and second NMOS transistors (N1 and N2). The current mirror controls the current sourcing and sinking capability of the translator. Third and fourth NMOS transistors (N3 and N4) are coupled to the first and second NMOS transistors in the current mirror and function to vary the source-to-body voltage of the first and second NMOS transistors and consequently their gain which results in increased current drive and sinking capability. The BiCMOS differential buffer of the present invention provides a differential output signal on first and second output nodes (115 and 215). It is comprised of first and second cross-coupled buffers (100B and 200B). Cross-coupling the buffers results in improved high-to-low transition times.

    BIPOLAR JUNCTION TRANSISTOR EXHIBITING SUPPRESSED KIRK EFFECT
    203.
    发明公开
    BIPOLAR JUNCTION TRANSISTOR EXHIBITING SUPPRESSED KIRK EFFECT 失效
    双极WITHOUT克尔克效应。

    公开(公告)号：EP0628215A1

    公开(公告)日：1994-12-14

    申请号：EP93905013.0

    申请日：1993-02-10

    Applicant: MicroUnity Systems Engineering, Inc.

    Inventor： MATTHEWS, James, A.

    IPC: H01L29 ,  H01L21

    CPC classification number: H01L29/66272 ,  H01L21/8249 ,  H01L29/0826 ,  Y10S257/927

    Abstract: Un transistor bipolaire à jonctions (TBJ) à effet Kirk supprimé comprend une région collectrice (11) de type n légèrement dopée formée sur une couche n+ (12) plus fortement dopée. Directement sur le collecteur se trouve une base de type p présentant une région extrinsèque (17) disposée latéralement autour d'une région intrinsèque (18). Un émetteur n+ (20) est positionné directement au-dessus de la région de base intrinsèque. Le TBJ comprend également une région n+ (15) localisée située directement au-dessous de la région de base intrinsèque, laquelle accroît significativement les capacités de traitement de courant du transistor.

Patent Agency Ranking