公开(公告)号：WO1995005033A1

公开(公告)日：1995-02-16

申请号：PCT/US1994004613

申请日：1994-04-28

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  WONG, Ban, Pak

IPC: H03K19/018

CPC classification number: H03K19/017563 ,  H03K19/013 ,  H03K19/01831

Abstract: An apparatus for reducing transmisson delay times when transmitting differential signals in an integrated circuit along long interconnect lines (10, 11) includes a current mode line driver which converts the differential signal to be transmitted into a signal that has a relatively low peak-to-peak voltage and large differential current changes. A receiver responsive to differential current changes converts the signal back into an output differential signal having peak-to-peak voltages adaptable to subsequent logic stages. A feedback circuit (Q5, Q6) coupled to the interconnect lines (10, 11) and the receiver functions to clamp the interconnect lines (10, 11) to a predetermined voltage while allowing the output differential signal to have peak-to-peak voltages greater than the predetermined voltage.

Abstract translation: 一种用于在沿着长互连线（10,11）的集成电路中传输差分信号时减小透射延迟时间的装置包括：电流模式线驱动器，其将待传输的差分信号转换成具有相对低的峰 - 峰值电压和大差分电流变化。 响应于差分电流变化的接收器将信号反馈回具有适应于后续逻辑级的峰 - 峰电压的输出差分信号。 耦合到互连线（10,11）的反馈电路（Q5，Q6）和接收器用于将互连线（10,11）钳位到预定电压，同时允许输出差分信号具有峰 - 峰电压 大于预定电压。

公开(公告)号：WO1994005085A1

公开(公告)日：1994-03-03

申请号：PCT/US1993005106

申请日：1993-05-28

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  WONG, Ban, Pak

IPC: H03K19/0944

CPC classification number: H03K19/018521 ,  H03K19/00361 ,  H03K19/0136 ,  H03K19/017518

Abstract: An ECL-to-CMOS level translator and BiCMOS buffer are described. The current supplied from the first input PMOS transistor (P1) is the input current to a current mirror comprising the first and second NMOS transistors (N1 and N2). The current mirror controls the current sourcing and sinking capability of the translator. Third and fourth NMOS transistors (N3 and N4) are coupled to the first and second NMOS transistors in the current mirror and function to vary the source-to-body voltage of the first and second NMOS transistors and consequently their gain which results in increased current drive and sinking capability. The BiCMOS differential buffer of the present invention provides a differential output signal on first and second output nodes (115 and 215). It is comprised of first and second cross-coupled buffers (100B and 200B). Cross-coupling the buffers results in improved high-to-low transition times.

Abstract translation: 描述了ECL到CMOS电平转换器和BiCMOS缓冲器。 从第一输入PMOS晶体管（P1）提供的电流是包括第一和第二NMOS晶体管（N1和N2）的电流镜的输入电流。 当前镜像控制翻译器的当前采样和下载功能。 第三和第四NMOS晶体管（N3和N4）耦合到电流镜中的第一和第二NMOS晶体管，并且用于改变第一和第二NMOS晶体管的源极体电压，并因此改变其增益，从而导致电流增加 驱动和下沉能力。 本发明的BiCMOS差分缓冲器在第一和第二输出节点（115和215）上提供差分输出信号。 它由第一和第二交叉耦合缓冲器（100B和200B）组成。 交叉耦合缓冲区导致改进的高到低的转换时间。

公开(公告)号：EP0739552A1

公开(公告)日：1996-10-30

申请号：EP94915426.0

申请日：1994-04-28

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： WONG, Ban, Pak

IPC: H03K19

CPC classification number: H03K19/017563 ,  H03K19/013 ,  H03K19/01831

Abstract: An apparatus for reducing transmisson delay times when transmitting differential signals in an integrated circuit along long interconnect lines (10, 11) includes a current mode line driver which converts the differential signal to be transmitted into a signal that has a relatively low peak-to-peak voltage and large differential current changes. A receiver responsive to differential current changes converts the signal back into an output differential signal having peak-to-peak voltages adaptable to subsequent logic stages. A feedback circuit (Q5, Q6) coupled to the interconnect lines (10, 11) and the receiver functions to clamp the interconnect lines (10, 11) to a predetermined voltage while allowing the output differential signal to have peak-to-peak voltages greater than the predetermined voltage.

公开(公告)号：EP0655177A1

公开(公告)日：1995-05-31

申请号：EP93914239.0

申请日：1993-05-28

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： WONG, Ban, Pak

IPC: H03K19

CPC classification number: H03K19/018521 ,  H03K19/00361 ,  H03K19/0136 ,  H03K19/017518

Abstract: An ECL-to-CMOS level translator and BiCMOS buffer are described. The current supplied from the first input PMOS transistor (P1) is the input current to a current mirror comprising the first and second NMOS transistors (N1 and N2). The current mirror controls the current sourcing and sinking capability of the translator. Third and fourth NMOS transistors (N3 and N4) are coupled to the first and second NMOS transistors in the current mirror and function to vary the source-to-body voltage of the first and second NMOS transistors and consequently their gain which results in increased current drive and sinking capability. The BiCMOS differential buffer of the present invention provides a differential output signal on first and second output nodes (115 and 215). It is comprised of first and second cross-coupled buffers (100B and 200B). Cross-coupling the buffers results in improved high-to-low transition times.