公开(公告)号：WO2006064961A1

公开(公告)日：2006-06-22

申请号：PCT/JP2005/023429

申请日：2005-12-14

Applicant: SONY COMPUTER ENTERTAINMENT INC.

Inventor： YAMAZAKI, Takeshi

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/10 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/651 ,  G06F2212/652

Abstract: Methods and apparatus provide for using a first portion of an external address as a pointer to select one of a plurality of entries in a segment table, each entry of the segment table representing a different segment of a memory; using at least a portion of the selected entry of the segment table as a reference to one or more of a plurality of entries in a page table, each entry in the page table including at least a portion of a physical address in the memory and belonging to a group of entries representing a page in the selected segment of the memory; and using a second portion of the external address as a pointer to one of the entries in the page table to obtain an at least partially translated physical address into the memory for the external address.

Abstract translation: 方法和装置提供使用外部地址的第一部分作为指针来选择段表中的多个条目中的一个，段表的每个条目表示存储器的不同段; 使用片段表的所选条目的至少一部分作为对页表中的多个条目中的一个或多个的引用，页表中的每个条目包括存储器中的物理地址的至少一部分并且属于 到表示存储器的所选段中的页面的一组条目; 以及使用外部地址的第二部分作为指向页表中的一个条目的指针，以获得用于外部地址的存储器中的至少部分转换的物理地址。

公开(公告)号：WO2006027021A1

公开(公告)日：2006-03-16

申请号：PCT/EP2004/011079

申请日：2004-09-10

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ANSCHEL, Moshe ,  BACHAR, Moshe ,  DAYAN, Uri ,  EFRAT, Jacob ,  PELED, Itay ,  ROZENSHEIN, Zvika

Inventor： ANSCHEL, Moshe ,  BACHAR, Moshe ,  DAYAN, Uri ,  EFRAT, Jacob ,  PELED, Itay ,  ROZENSHEIN, Zvika

IPC: G06F12/14

CPC classification number: G06F12/1036 ,  G06F12/1483 ,  G06F12/1491

Abstract: A memory management unit that includes: (i) multiple data segment descriptors, each data segment descriptor associated with a data memory segment; (ii) multiple program segment descriptors, each program segment descriptor associated with a program memory segment; and (iii) a controller, adapted to replace the content of the multiple data segment descriptors in response to a task switch. A method for memory management, the method includes: (i) providing multiple data segment descriptors; each data segment descriptor associated with a data memory segment, and providing multiple program segment descriptors, each program segment descriptor associated with a program memory segment; (ii) receiving and storing a program task identifier and a data task identifier; (iii) receiving a data access request and determining how to handle the data access request in response to a content of the multiple data segment descriptors; and (iv) receiving a program access request and determining how to handle the program access request in response to a content of the multiple program segment descriptors.

Abstract translation: 一种存储器管理单元，包括：（i）多个数据段描述符，每个数据段描述符与数据存储段相关联; （ii）多个节目段描述符，每个节目段描述符与节目存储段相关联; 以及（iii）控制器，适于响应于任务切换来替换所述多个数据段描述符的内容。 一种用于存储器管理的方法，所述方法包括：（i）提供多个数据段描述符; 每个数据段描述符与数据存储器段相关联，并且提供多个程序段描述符，每个程序段描述符与程序存储段相关联; （ii）接收和存储程序任务标识符和数据任务标识符; （iii）响应于所述多个数据段描述符的内容，接收数据访问请求并确定如何处理所述数据访问请求; 以及（iv）接收程序访问请求并且响应于所述多个节目段描述符的内容来确定如何处理所述节目访问请求。

公开(公告)号：WO2004066093A3

公开(公告)日：2005-05-06

申请号：PCT/US2004001711

申请日：2004-01-21

Applicant: INTELITRAC INC

Inventor： CHEN TIANLONG ,  VU JONATHON ,  WANG YINGBIN

IPC: G06F20060101 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/10 ,  G11C11/22

CPC classification number: G06F12/0284 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2056 ,  G06F11/2069 ,  G06F12/1036 ,  G06F12/1072

Abstract: A Distributed Memory Computing Environment (herein called "DMCE") architecture and implementation is disclosed in which any computer equipped with a memory agent can borrow memory from other computer(s) equipped with a memory server on a distributed network. A memory backup and recovery as an optional subsystem of the Distributed Memory Computing system is also disclosed. A Network Attached Memory (herein called "NAM" or "NAM Box" or "NAM Server") appliance is disclosed as a dedicated memory-sharing device attached to a network. A Memory Area Network (herein called "MAN") is further disclosed, such a network is a network of memory device(s) or memory server(s) which provide memory sharing service to memory-demanding computer(s) or the like, when one memory device or memory server fails, its service will seamlessly transfer to other memory device(s) or memory server(s).

Abstract translation: 公开了一种分布式存储器计算环境（这里称为“DMCE”）架构和实现方式，其中配备有存储器代理的任何计算机可以借用来自在分布式网络上配备有存储器服务器的其它计算机的存储器。 还公开了作为分布式存储器计算系统的可选子系统的存储器备份和恢复。 网络连接存储器（这里称为“NAM”或“NAM盒”或“NAM服务器”）设备被公开为附接到网络的专用存储器共享设备。 进一步公开了存储器区域网络（这里称为“MAN”），这样的网络是向存储器要求苛刻的计算机等提供存储器共享服务的存储器设备或存储器服务器的网络， 当一个存储设备或存储器服务器出现故障时，其服务将无缝传输到其他存储设备或存储器服务器。

公开(公告)号：WO1993000636A1

公开(公告)日：1993-01-07

申请号：PCT/US1992005351

申请日：1992-06-25

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  MASON, Andrew, H. ,  HALL, Judith, S. ,  WITEK, Richard, T. ,  ROBINSON, Paul, T.

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/1054 ,  G06F12/109 ,  G06F2212/656

Abstract: A CPU executing a virtual memory management system employs a translation buffer for catching recently used page table entries. When more than one process is executing on the CPU, the translation buffer is usually flushed when a context switch is made, even though some of the entries would still be valid for commonly-referenced memory areas. An address space number feature is employed to allow entries to remain in the translation buffer for processes not currently executing, and the separate processes or the operating system can reuse entries in the translation buffer for such pages of memory that are commonly referenced. To allow this, an "address space match" entry in the page table entry signals that the translation buffer content can be used when the address tag matches, even though the address space numbers do not necessarily match. When executing virtual machines on this CPU, with a virtual machine monitor, the address space match feature is employed among processes of a virtual machine, but an additional entry is provided to disable the address space match feature for all address space numbers for the virtual machine monitor.

Abstract translation: 执行虚拟存储器管理系统的CPU采用翻译缓冲器来捕获最近使用的页表项。 当CPU上执行多个进程时，即使某些条目对于常用引用的内存区域仍然有效，通常在进行上下文切换时刷新翻译缓冲区。 采用地址空间编号特征来允许条目保留在翻译缓冲器中用于当前未执行的进程，并且单独的进程或操作系统可以重用翻译缓冲器中用于通常引用的这种存储器页面的条目。 为了允许这一点，页表项目中的“地址空间匹配”条目表示当地址标签匹配时可以使用翻译缓冲器内容，即使地址空间号码不一定匹配。 当在这个CPU上执行虚拟机时，使用虚拟机监视器，在虚拟机的进程中采用地址空间匹配功能，但是提供了一个附加条目来禁用虚拟机的所有地址空间编号的地址空间匹配功能 监控。

公开(公告)号：WO2016195869A1

公开(公告)日：2016-12-08

申请号：PCT/US2016/030040

申请日：2016-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： PODAIMA, Jason, Edward ,  RYCHLIK, Bohuslav ,  MOREIRA, Carlos, Javier ,  GADELRAB, Serag, Monier ,  WIERCIENSKI, Paul, Christopher John ,  MIRETSKY, Alexander ,  ERNEWEIN, Kyle, John

IPC: G06F12/1036 ,  G06F12/109

CPC classification number: G06F12/0848 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/50 ,  G06F2212/601 ,  G06F2212/68 ,  G06F2212/70 ,  Y02D10/13

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, in one aspect, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

Abstract translation: 提供存储器管理单元（MMU）分区转换高速缓存，以及相关设备，方法和计算机可读介质。 在这方面，在一方面，提供了包括MMU的装置。 MMU包括提供定义地址转换映射的多个转换高速缓存条目的翻译高速缓存。 所述MMU还包括分区描述符表，其提供多个分区描述符，所述分区描述符定义相应的多个分区，每个分区包括所述多个转换高速缓存条目中的一个或多个转换高速缓存条目。 MMU还包括被配置为从请求者接收存储器访问请求的分区转换电路。 分区转换电路还被配置为确定存储器访问请求的翻译高速缓存分区标识符（TCPID），基于TCPID识别多个分区中的一个或多个分区，并且在翻译高速缓存条目上执行存储器访问请求 一个或多个分区。

公开(公告)号：WO2016175814A1

公开(公告)日：2016-11-03

申请号：PCT/US2015/028418

申请日：2015-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： LILLIBRIDGE, Mark David ,  FARABOSCHI, Paolo

IPC: G06F12/08 ,  G06F12/06

CPC classification number: G06F12/1036 ,  G06F12/023 ,  G06F12/0292 ,  G06F12/0804 ,  G06F2212/1012 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/302 ,  G06F2212/455 ,  G06F2212/657

Abstract: Apertures of a first size in a first physical address space of at least one processor are mapped to respective blocks of the first size in a second address space of a storage medium. Apertures of a second size in the first physical address space are mapped to respective blocks of the second size in the second address space, the second size being different from the first size.

Abstract translation: 至少一个处理器的第一物理地址空间中的第一大小的孔径被映射到存储介质的第二地址空间中的第一大小的相应块。 第二物理地址空间中的第二大小的孔径被映射到第二地址空间中的第二大小的相应块，第二大小与第一大小不同。

公开(公告)号：WO2014058762A3

公开(公告)日：2014-07-10

申请号：PCT/US2013063651

申请日：2013-10-07

Applicant: IBM

Inventor： GSCHWIND MICHAEL

IPC: G06F13/36

CPC classification number: G06F12/1009 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/0671 ,  G06F3/0673 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/0292 ,  G06F12/1018 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/109 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/151 ,  G06F2212/657 ,  G06F2212/7201 ,  G06F2212/7202

Abstract: A system configuration is provided with multiple partitions that supports different types of address translation structure formats. The configuration may include partitions that use a single level of translation and those that use a nested level of translation. Further, differing types of translation structures may be used. The different partitions are supported by a single hypervisor.

Abstract translation: 系统配置提供多个分区，支持不同类型的地址转换结构格式。 配置可能包括使用单一级别转换的分区和使用嵌套级别转换的分区。 此外，可以使用不同类型的翻译结构。 不同的分区由单个管理程序支持。

公开(公告)号：WO2014004151A3

公开(公告)日：2014-03-13

申请号：PCT/US2013046169

申请日：2013-06-17

Applicant: INTEL CORP ,  HILDESHEIM GUR ,  RAIKIN SHLOMO ,  ANATI ITTAI ,  GERZON GIDEON ,  SAVAGAONKAR UDAY ,  MCKEEN FRANCIS ,  ROZAS CARLOS ,  GOLDSMITH MICHAEL ,  DEWAN PRASHANT

Inventor： HILDESHEIM GUR ,  RAIKIN SHLOMO ,  ANATI ITTAI ,  GERZON GIDEON ,  SAVAGAONKAR UDAY ,  MCKEEN FRANCIS ,  ROZAS CARLOS ,  GOLDSMITH MICHAEL ,  DEWAN PRASHANT

IPC: G06F12/08

CPC classification number: G06F12/109 ,  G06F12/0284 ,  G06F12/1036 ,  G06F2212/656 ,  G06F2212/657

Abstract: Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.

Abstract translation: 公开了包括虚拟地址存储器范围寄存器的装置和方法的实施例。 在一个实施例中，处理器包括存储器接口，地址转换硬件和虚拟存储器地址比较硬件。 存储器接口使用物理存储器地址访问系统存储器。 地址转换硬件支持将虚拟存储器地址转换为物理存储器地址。 虚拟内存地址被软件用来访问处理器的虚拟内存地址空间中的虚拟内存位置。 虚拟内存地址比较硬件用于确定虚拟内存地址是否在虚拟内存地址范围内。

公开(公告)号：WO2014031495A2

公开(公告)日：2014-02-27

申请号：PCT/US2013055451

申请日：2013-08-16

Applicant: ARTERIS SAS ,  MOLL LAURENT ,  LECLER JEAN-JACQUES ,  BOUCARD PHILIPPE

Inventor： MOLL LAURENT ,  LECLER JEAN-JACQUES ,  BOUCARD PHILIPPE

IPC: G06F12/02 ,  G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/0207 ,  G06F12/0215 ,  G06F12/0811 ,  G06F12/1027 ,  G06F12/1081 ,  G06F17/5009 ,  G06F2212/681

Abstract: A system TLB accepts translation prefetch requests from initiators. Misses generate external translation requests to a walker port. Attributes of the request such as ID, address, and class, as well as the state of the TLB affect the allocation policy of translations within multiple levels of translation tables. Translation tables are implemented with SRAM, and organized in groups.

Abstract translation: 系统TLB接受来自发起者的翻译预取请求。 Misses会向Walker端口生成外部翻译请求。 诸如ID，地址和类的请求的属性以及TLB的状态会影响多级翻译表中的翻译分配策略。 翻译表用SRAM实现，并组织成组。

公开(公告)号：WO2013101378A1

公开(公告)日：2013-07-04

申请号：PCT/US2012/066753

申请日：2012-11-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BHOWMIK, Prasanta, K. ,  HUNT, Douglas, B.

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F2212/651 ,  G06F2212/684

Abstract: A translation lookaside buffer (TLB) configured for use in a multiple operating system environment includes a plurality of storage locations, each storage location being configured to store a page translation entry configured to relate a virtual address range to a physical address range, each page translation entry having an address space identifier (ASID) associated with an operating system. The TLB also includes flush logic configured to receive a TLB flush request from an operating system having an operating system ASID and flush only TLB page translation entries having a stored ASID that matches the operating system ASID.

Abstract translation: 被配置为在多操作系统环境中使用的翻译后备缓冲器（TLB）包括多个存储位置，每个存储位置被配置为存储被配置为将虚拟地址范围与物理地址范围相关联的页面翻译条目， 条目具有与操作系统相关联的地址空间标识符（ASID）。 TLB还包括被配置为从具有操作系统ASID的操作系统接收TLB刷新请求并且仅刷新具有与操作系统ASID匹配的存储的ASID的TLB页面转换条目的刷新逻辑。