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    FIREWALL TO DETERMINE ACCESS TO A PORTION OF MEMORY
    1.
    发明申请
    FIREWALL TO DETERMINE ACCESS TO A PORTION OF MEMORY 审中-公开
    防止访问存储器的一部分

    公开(公告)号：WO2017019061A1

    公开(公告)日：2017-02-02

    申请号：PCT/US2015/042661

    申请日：2015-07-29

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： LILLIBRIDGE, Mark ,  FARABOSCHI, Paolo ,  DALTON, Chris I.

    IPC: G06F12/14

    CPC classification number: G06F21/70 ,  G06F3/0622 ,  G06F3/0659 ,  G06F3/0673 ,  G06F21/53 ,  G06F21/74

    Abstract: Techniques for a firewall to determine access to a portion of memory are provided. In one aspect, an access request to access a portion of memory within a pool of shared memory may be received at a firewall. The firewall may determine whether the access request to access the portion of memory is allowed. The access request may be allowed to proceed based on the determination. The operation of the firewall may not utilize address translation.

    Abstract translation: 提供了防火墙确定访问一部分内存的技术。 在一个方面，可以在防火墙处接收访问共享存储器池中的一部分存储器的访问请求。 防火墙可以确定是否允许访问存储器部分的访问请求。 可以基于确定来允许访问请求进行。 防火墙的操作可能不会利用地址转换。

    ALLOCATING COHERENT AND NON-COHERENT MEMORIES
    4.
    发明申请
    ALLOCATING COHERENT AND NON-COHERENT MEMORIES 审中-公开
    分配相干和非相干记忆

    公开(公告)号：WO2017135962A1

    公开(公告)日：2017-08-10

    申请号：PCT/US2016/016759

    申请日：2016-02-05

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： DAGLIS, Alexandros ,  FARABOSCHI, Paolo

    IPC: G06F12/02

    CPC classification number: G06F13/1663

    Abstract: A computing device includes a coherence controller and memory comprising a coherent memory region and a non-coherent memory region. The coherence controller may: determine a coherent region of the memory, determine a non-coherent region of the memory, and responsive to receiving a memory allocation request for a block of memory in the memory: allocate, based on a received memory allocation request for a memory block, the requested block of memory in the non-coherent memory region or the coherent memory region based on whether the memory allocation request indicates the requested block is to be coherent or non-coherent.

    Abstract translation: 计算设备包括相干控制器和存储器，存储器包括相干存储器区域和非相干存储器区域。 相干性控制器可以：确定存储器的相干区域，确定存储器的非相干区域，并且响应于接收到存储器中的存储器块的存储器分配请求：基于接收到的存储器分配请求 存储器块，基于存储器分配请求是否指示所请求的块，在非一致性存储器区域或一致性存储器区域中所请求的存储器块将是一致的或非一致的。

    MEMORY NETWORK TO PRIORITIZE PROCESSING OF A MEMORY ACCESS REQUEST
    5.
    发明申请
    MEMORY NETWORK TO PRIORITIZE PROCESSING OF A MEMORY ACCESS REQUEST 审中-公开
    存储器访问存储器优先处理存储器网络

    公开(公告)号：WO2016122662A1

    公开(公告)日：2016-08-04

    申请号：PCT/US2015/013969

    申请日：2015-01-30

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： TALWAR, Vanish ,  FARABOSCHI, Paolo ,  GMACH, Daniel Juergen ,  CHEN, Yuan ,  DAVIS, Alan Lynn ,  MADAN, Adit

    IPC: G06F15/173

    CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/067 ,  G06F15/17331

    Abstract: In one example, a memory network may control access to a shared memory that is by multiple compute nodes. The memory network may control the access to the shared memory by receiving a memory access request originating from an application executing on the multiple compute nodes and determining a priority for processing the memory access request. The priority determined by the memory network may correspond to a memory address range in the memory that is specifically used by the application.

    Abstract translation: 在一个示例中，存储器网络可以控制对由多个计算节点进行的共享存储器的访问。 存储器网络可以通过接收从在多个计算节点上执行的应用程序产生的存储器访问请求来控制对共享存储器的访问，并且确定处理存储器访问请求的优先级。 由存储器网络确定的优先级可以对应于由应用专门使用的存储器中的存储器地址范围。

    CACHE MANAGER-CONTROLLED MEMORY ARRAY
    7.
    发明申请
    CACHE MANAGER-CONTROLLED MEMORY ARRAY 审中-公开
    高速缓存管理器控制的内存阵列

    公开(公告)号：WO2017091197A1

    公开(公告)日：2017-06-01

    申请号：PCT/US2015/062119

    申请日：2015-11-23

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： CAI, Qiong ,  FARABOSCHI, Paolo

    IPC: G06F12/08

    CPC classification number: G06F12/0873 ,  G06F12/0804 ,  G06F12/0848 ,  G06F2212/1024 ,  G06F2212/214

    Abstract: In an example, an apparatus is described that includes a memory array. The memory array includes a volatile memory, a first non-volatile memory, and a second non-volatile memory. The memory array further includes a cache manager that controls access by a computer system to the memory array. For instance, the cache manager may carry out memory operations, including read operations, write operations, and cache evictions, in conjunction with at least one of the volatile memory, the first non-volatile memory, or the second non-volatile memory.

    Abstract translation: 在一个示例中，描述了包括存储器阵列的装置。 存储器阵列包括易失性存储器，第一非易失性存储器和第二非易失性存储器。 存储器阵列进一步包括高速缓存管理器，其控制计算机系统对存储器阵列的访问。 例如，高速缓存管理器可以结合易失性存储器，第一非易失性存储器或第二非易失性存储器中的至少一个来执行包括读取操作，写入操作和高速缓存驱逐的存储器操作。 / p>

    DYNAMIC THREAD MAPPING
    9.
    发明申请
    DYNAMIC THREAD MAPPING 审中-公开
    动态线程映射

    公开(公告)号：WO2017188948A1

    公开(公告)日：2017-11-02

    申请号：PCT/US2016/029635

    申请日：2016-04-27

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： CAI, Qiong ,  JOHNSON, Charles ,  FARABOSCHI, Paolo

    IPC: G06F9/30 ,  G06F9/38

    Abstract: In one example, a central processing unit (CPU) with dynamic thread mapping includes a set of multiple cores each with a set of multiple threads. A set of registers for each of the multiple threads monitors for in-flight memory requests the number of loads from and stores to at least a first memory interface and a second memory interface by each respective thread. The second memory interface has a greater latency than the first memory interface. The CPU further has logic to map and migrate each thread to respective CPU cores where the number of cores accessing only one of the at least first and second memory interfaces is maximized.

    Abstract translation: 在一个示例中，具有动态线程映射的中央处理单元（CPU）包括一组多个核心，每个核心具有一组多个线程。 用于飞行存储器的多个线程监视器中的每一个的一组寄存器通过每个相应线程向至少第一存储器接口和第二存储器接口请求负载的数量。 第二个存储器接口比第一个存储器接口具有更大的延迟。 CPU还具有将每个线程映射和迁移到各个CPU核心的逻辑，其中仅访问至少第一和第二存储器接口中的一个的核心数量被最大化。

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