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公开(公告)号:WO2017019095A1
公开(公告)日:2017-02-02
申请号:PCT/US2015/042953
申请日:2015-07-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: LILLIBRIDGE, Mark David , GOSTIN, Gary , FARABOSCHI, Paolo , SHERLOCK, Derek Alan , RAY, Harvey
CPC classification number: G06F12/0607 , G06F2212/1016
Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.
Abstract translation: 在一些示例中,多个处理器的每个处理器应用交织变换来执行多个存储体的交织访问,其中对于多个处理器使用的任何给定存储器地址,应用任何交织变换导致选择 多个存储器组中的相同存储体和相同存储体内相同的地址。
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公开(公告)号:WO2016175814A1
公开(公告)日:2016-11-03
申请号:PCT/US2015/028418
申请日:2015-04-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: LILLIBRIDGE, Mark David , FARABOSCHI, Paolo
CPC classification number: G06F12/1036 , G06F12/023 , G06F12/0292 , G06F12/0804 , G06F2212/1012 , G06F2212/1016 , G06F2212/1041 , G06F2212/302 , G06F2212/455 , G06F2212/657
Abstract: Apertures of a first size in a first physical address space of at least one processor are mapped to respective blocks of the first size in a second address space of a storage medium. Apertures of a second size in the first physical address space are mapped to respective blocks of the second size in the second address space, the second size being different from the first size.
Abstract translation: 至少一个处理器的第一物理地址空间中的第一大小的孔径被映射到存储介质的第二地址空间中的第一大小的相应块。 第二物理地址空间中的第二大小的孔径被映射到第二地址空间中的第二大小的相应块,第二大小与第一大小不同。
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公开(公告)号:EP3256947A1
公开(公告)日:2017-12-20
申请号:EP15890946.5
申请日:2015-04-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor: LILLIBRIDGE, Mark David , FARABOSCHI, Paolo
CPC classification number: G06F12/1036 , G06F12/023 , G06F12/0292 , G06F12/0804 , G06F2212/1012 , G06F2212/1016 , G06F2212/1041 , G06F2212/302 , G06F2212/455 , G06F2212/657
Abstract: Apertures of a first size in a first physical address space of at least one processor are mapped to respective blocks of the first size in a second address space of a storage medium. Apertures of a second size in the first physical address space are mapped to respective blocks of the second size in the second address space, the second size being different from the first size.
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公开(公告)号:EP3271826A1
公开(公告)日:2018-01-24
申请号:EP15899885.6
申请日:2015-07-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor: LILLIBRIDGE, Mark David , GOSTIN, Gary , FARABOSCHI, Paolo , SHERLOCK, Derek Alan , RAY, Harvey
CPC classification number: G06F12/0607 , G06F3/0611 , G06F3/0644 , G06F3/0659 , G06F3/0673 , G06F2212/1016 , G06F2212/1024
Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.
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