公开(公告)号：US06268229B1

公开(公告)日：2001-07-31

申请号：US09461693

申请日：1999-12-14

Applicant: George R. Brandes ,  Charles P. Beetz ,  Xueping Xu ,  Swayambu V. Ramani ,  Ronald S. Besser

Inventor： George R. Brandes ,  Charles P. Beetz ,  Xueping Xu ,  Swayambu V. Ramani ,  Ronald S. Besser

IPC: H01L2100

CPC classification number: H01L28/20 ,  H01J1/3042 ,  H01J2201/30403 ,  H01J2201/319 ,  H01J2329/00 ,  H01L31/03765 ,  Y02E10/548 ,  Y10S438/931

Abstract: Integrated circuits, including field emission devices, have a resistor element of amorphous SixC1-x wherein 0

Abstract translation: 包括场致发射器件的集成电路具有0≤x≤1的无定形六C1-x的电阻元件，并且其中所述SixC1-x包含选自氢，卤素，氮，氧，硫中的至少一种杂质 ，硒，过渡金属，硼，铝，磷，镓，砷，锂，铍，钠和镁。

公开(公告)号：US06194308B1

公开(公告)日：2001-02-27

申请号：US09421165

申请日：1999-10-19

Applicant: Everett A. McTeer ,  Russell C. Zahorik ,  Scott G. Meikle

Inventor： Everett A. McTeer ,  Russell C. Zahorik ,  Scott G. Meikle

IPC: H01L310232

CPC classification number: H01L21/76849 ,  H01J1/52 ,  H01J29/896 ,  H01J31/127 ,  H01J2201/30403 ,  H01J2201/319 ,  H01L21/0276 ,  H01L21/32139 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/76885 ,  H01L23/53223 ,  H01L31/02161 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Titanium aluminum nitrogen (“Ti—Al—N”) is deposited onto a semiconductor substrate area to serve as an antireflective coating. For wiring line fabrication processes, the Ti—Al—N layer serves as a cap layer which prevents unwanted reflection of photolithography light (i.e., photons) during fabrication. For field emission display devices (FEDs), the Ti—Al—N layer prevents light originating at the display screen anode from penetrating transistor junctions that would hinder device operation. For the wiring line embodiment, an aluminum conductive layer and a titanium-aluminum underlayer are formed beneath the antireflective cap layer. The Ti—Al underlayer reduces the shrinkage which occurs in the aluminum conductive layer during heat treatment.

Abstract translation: 将钛铝氮（“Ti-Al-N”）沉积到半导体衬底区域上以用作抗反射涂层。 对于布线生产工艺，Ti-Al-N层用作遮盖层，防止在制造过程中光刻光（即光子）的不期望的反射。 对于场致发射显示装置（FED），Ti-Al-N层防止在显示屏阳极处产生的光穿透将阻碍器件工作的晶体管结。 对于布线实施例，在抗反射盖层下方形成铝导电层和钛 - 铝底层。 Ti-Al底层减少了在热处理期间在铝导电层中发生的收缩。

公开(公告)号：US06187604B1

公开(公告)日：2001-02-13

申请号：US08864496

申请日：1997-05-28

Applicant: Terry L. Gilton

Inventor： Terry L. Gilton

IPC: H01L200

CPC classification number: H01J9/025 ,  H01J2201/30403 ,  H01J2209/0226

Abstract: A process is provided for forming sharp asperities, useful as field emitters. The process comprises: patterning and doping a silicon substrate. The doped silicon substrate is anodized. The anodized area is then used for field emission tips. The process of the present invention is also useful for low temperature sharpening of tips fabricated by other methods. The tips are anodized, and then exposed to radiant energy, and the resulting oxide is removed.

Abstract translation: 提供了用于形成尖锐凹凸的工艺，可用作场致发射体。 该方法包括：图案化和掺杂硅衬底。 掺杂硅衬底被阳极氧化。 然后将阳极氧化区域用于场发射尖端。 本发明的方法也可用于通过其它方法制造的尖端的低温磨削。 将尖端进行阳极氧化，然后暴露于辐射能，并将所得氧化物除去。

公开(公告)号：US6126845A

公开(公告)日：2000-10-03

申请号：US354923

申请日：1999-07-15

Applicant: David A. Cathey ,  Kevin Tjaden

Inventor： David A. Cathey ,  Kevin Tjaden

IPC: H01J9/02 ,  B44C1/22 ,  H01J9/00

CPC classification number: H01J9/025 ,  H01J2201/30403

Abstract: A method for fabricating sharp asperities. A substrate is provided which has a mask layer disposed thereon, and a layer of micro-spheres is disposed superjacent the mask layer. The micro-spheres are for patterning the mask layer. Portions of the mask layer are selectively removed, thereby forming circular masks. The substrate is isotropically etched, thereby creating sharp asperities.

Abstract translation: 一种制造尖锐凹凸的方法。 提供了具有设置在其上的掩模层的基板，并且在该掩模层的上方布置一层微球。 微球用于图案化掩模层。 选择性地去除掩模层的一部分，从而形成圆形掩模。 基板被各向同性地蚀刻，从而产生尖锐的凹凸。

公开(公告)号：US6049089A

公开(公告)日：2000-04-11

申请号：US161338

申请日：1998-09-25

Applicant: David A. Cathey

Inventor： David A. Cathey

IPC: H01J1/304 ,  H01J9/02 ,  H01J9/04

CPC classification number: H01J1/3044 ,  H01J1/3042 ,  H01J9/025 ,  H01J2201/30403 ,  Y10S148/116 ,  Y10S148/172 ,  Y10S438/978

Abstract: Electron emitters and a method of fabricating emitters which have a concentration gradient of impurities, such that the highest concentration of impurities is at the apex of the emitters, and decreases toward the base of the emitters. The method comprises the steps of doping, patterning, etching, and oxidizing the substrate, thereby forming the emitters having impurity gradients.

公开(公告)号：US6031250A

公开(公告)日：2000-02-29

申请号：US575484

申请日：1995-12-20

Applicant: George R. Brandes ,  Charles P. Beetz ,  Xueping Xu ,  Swayambu V. Ramani ,  Ronald S. Besser

Inventor： George R. Brandes ,  Charles P. Beetz ,  Xueping Xu ,  Swayambu V. Ramani ,  Ronald S. Besser

IPC: H01J9/02 ,  H01J1/304 ,  H01J19/24 ,  H01J21/10 ,  H01J29/04 ,  H01J31/12 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L31/0376 ,  H01L31/0312

CPC classification number: H01L28/20 ,  H01J1/3042 ,  H01L31/03765 ,  H01J2201/30403 ,  H01J2201/319 ,  H01J2329/00 ,  Y02E10/548 ,  Y10S438/931

Abstract: Integrated circuits, including field emission devices, have a resistor element of amorphous Si.sub.x C.sub.1-x wherein 0

Abstract translation: 包括场致发射器件的集成电路具有0≤x≤1的无定形六C1-x的电阻元件，并且其中所述SixC1-x包含选自氢，卤素，氮，氧，硫中的至少一种杂质 ，硒，过渡金属，硼，铝，磷，镓，砷，锂，铍，钠和镁。

公开(公告)号：US5939822A

公开(公告)日：1999-08-17

申请号：US914291

申请日：1997-08-18

Applicant: Richard K. Alderson

Inventor： Richard K. Alderson

IPC: H01J29/02 ,  H01J29/86 ,  H01J31/12 ,  H01J1/62

CPC classification number: H01J31/123 ,  H01J29/864 ,  H01J31/127 ,  H01J2201/025 ,  H01J2201/30403 ,  H01J2329/863 ,  H01J2329/8635 ,  H01J2329/864 ,  H01J2329/8645

Abstract: A support structure is provided that enables the use of high-voltage phosphors in field-emission flat panel displays, to maintain the vacuum gap between the cathode and the anode at a constant distance and to prevent distortion of the transparent view screen and backing plate of the display. A number of independent techniques each contributes to the solution of the problem of secondary electron emission. One technique is to alter the geometry of the triple junction of the support structure, the cathode, and the vacuum gap, thereby reducing the electrostatic field created at the triple junction. Reducing the electrostatic field reduces the initial primary electron bombardment originating at the triple junction. Altering the geometry of the support surface with respect to the field lines present at the triple junction also increases the probability that impinging electrons will impact at or nearly at right angles, and will also tend to be directed by the field lines back into the "pocket" created by the shaping of the support structure edge, preventing secondary electrons from escaping and traveling along the structure surface to the anode. In accordance with another technique, the support structure is fluted so as to reduce the average coefficient of secondary electron emission, to trap a proportion of secondary electrons, and to limit the number of hops of other secondary electrons. In another technique, a high resistivity conductive layer is formed at the triple junction in order to reduce the field potential at the triple junction. A similar conductive layer may be formed at the opposite junction of the support structure, the anode, and the vacuum gap. A high resistivity conductive material coated on the surface of the insulating spacer can be used to decrease the charge relaxation time of the insulator, thereby maintaining a constant field potential over the surface of the insulator, reducing areas of high field potential which will tend to accelerate secondary electron emissions. In accordance with other techniques, the support structure is made of a non-porous material and may be coated with a coating having low secondary emission characteristics.

公开(公告)号：US5913704A

公开(公告)日：1999-06-22

申请号：US855425

申请日：1997-05-12

Applicant: Christopher J. Spindt ,  John M. Macaulay ,  Robert M. Duboc, Jr. ,  Peter C. Searson

Inventor： Christopher J. Spindt ,  John M. Macaulay ,  Robert M. Duboc, Jr. ,  Peter C. Searson

IPC: H01J1/30 ,  H01J1/304 ,  H01J3/02 ,  H01J9/02 ,  H01J29/04 ,  H01J31/12

CPC classification number: B82Y10/00 ,  H01J1/3042 ,  H01J3/022 ,  H01J9/025 ,  H01J2201/30403 ,  H01J2201/30457 ,  H01J2201/319

Abstract: Gated electron emitters are fabricated by processes in which charged particles are passed through a track layer (24, 48, or 144) to form charged-particle tracks (26.sub.1, 50.sub.1, or 146.sub.1). The track layer is etched along the tracks to create open spaces (28.sub.1, 52.sub.1, or 148.sub.1). Electron-emissive elements (30 or 142D) can then be formed at locations respectively centered on the open spaces after which a patterned gate layer (34B, 40B, or 158C) is provided. Alternatively, the open spaces in the track layer can be employed to etch corresponding apertures (54.sub.1) through an underlying non-insulating layer (46) which typically serves as the gate layer. An etch is performed through the apertures to form dielectric open spaces (56.sub.1, 96.sub.1, or 114.sub.1) in an insulating layer (24) that lies below the non-insulating layer. Electron-emissive elements (30B, 30/88D.sub.1, 98/102.sub.1, or 118.sub.1) can subsequently be provided, typically in the dielectric open spaces.

Abstract translation: 门电子发射器通过其中带电粒子通过轨道层（24,48或144）以形成带电粒子轨道（261,501或1461）的工艺制造。 轨道层沿着轨道被蚀刻以创建开放空间（281,521或1481）。 然后可以在分开以开放空间为中心的位置处形成电子发射元件（30或142D），之后设置图案化栅极层（34B，40B或158C）。 或者，轨道层中的开放空间可用于通过通常用作栅极层的下面的非绝缘层（46）蚀刻相应的孔（541）。 通过孔进行蚀刻，以在位于非绝缘层下方的绝缘层（24）中形成介电开放空间（561,961或1141）。 随后可以提供电子发射元件（30B，30 / 88D1,98 / 1011或1181），通常在电介质开放空间中。

公开(公告)号：US5860844A

公开(公告)日：1999-01-19

申请号：US962735

申请日：1997-11-03

Applicant: Masato Susukida ,  Jun Hagiwara ,  Katsuto Nagano

Inventor： Masato Susukida ,  Jun Hagiwara ,  Katsuto Nagano

IPC: H01J1/304 ,  H01J9/02

CPC classification number: H01J9/025 ,  H01J1/3042 ,  H01J2201/30403 ,  H01J2201/30457

Abstract: A cold cathode electron source element having a cold cathode on a substrate. The cold cathode has dispersed in a cold cathode base particles of a conductive material having a lower work function than the base and a particle size which is sufficiently smaller than the thickness of the cold cathode. The element can be driven with a low voltage to induce high emission current in a stable manner. The cold cathode is easily processable. The element can have an increased surface area.

Abstract translation: 在基板上具有冷阴极的冷阴极电子源元件。 冷阴极已经分散在具有比碱低的功函数的导电材料的冷阴极基体颗粒中，并且其粒径足够小于冷阴极的厚度。 元件可以用低电压驱动，以稳定的方式感应高发射电流。 冷阴极易于加工。 元件可以具有增加的表面积。

公开(公告)号：US5847504A

公开(公告)日：1998-12-08

申请号：US690895

申请日：1996-08-01

Applicant: Livio Baldi

Inventor： Livio Baldi

IPC: G09G3/22 ,  H01J1/304 ,  H01J31/12 ,  H01J1/62 ,  H01J1/02 ,  H01J1/16 ,  H01J63/04

CPC classification number: G09G3/22 ,  H01J1/3042 ,  H01J31/127 ,  H01J2201/30403 ,  H01J2201/319 ,  H01J2329/00

Abstract: A pixel emission current limiting resistance is realized by forming a stack of alternately doped amorphous or polycrystalline silicon layers over the cathodic conductors of a FED driving matrix. The stack of amorphous or polycrystalline silicon layers doped alternately n and p provides at least a reversely biased n/p junction having a leakage current that matches the required level of pixel emission current. The reversely biased junction constitutes a nonlinear series resistance that is quite effective in limiting the emission current through any one of the microtips that form an individually excitable pixel and which are formed on the uppermost layer of the stack.

Abstract translation: 通过在FED驱动矩阵的阴极导体上形成交替掺杂的非晶或多晶硅层的堆叠来实现像素发射电流限制电阻。 掺杂交替地n和p的非晶或多晶硅层的堆叠提供至少一个具有与所要求的像素发射电流水平匹配的漏电流的反向偏置n / p结。 反向偏置的结构成非线性串联电阻，其非常有效地限制通过形成可单独激发的像素并且形成在堆叠的最上层上的任何一个微尖端的发射电流。