公开(公告)号：EP2126969B1

公开(公告)日：2012-06-27

申请号：EP08708288.9

申请日：2008-01-28

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L21/60 ,  H01L23/48 ,  H01L25/065 ,  H01L21/98

CPC classification number: H01L24/81 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16146 ,  H01L2224/81224 ,  H01L2224/8184 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  Y10T29/49126 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00 ,  H01L2924/00014

Abstract: The invention relates to a method of interconnecting electronic components of a first wafer (T1) with electronic components of a second wafer (T2), each wafer comprising metallized vias (1) which pass through the thickness of the wafer. The method comprises the following steps of: Depositing a drop (3) of conducting ink containing solvents and nanoparticles of metal onto each via (1) of the first wafer (T1), stacking the second wafer (T2) on the first in such a way that the vias (1) of the second wafer (T2) are substantially overlaid on the vias (1) of the first wafer (T1). Eliminating 50 to 90% of the solvents contained in the drops (3) by heating or vacuum treatment so as to obtain a pasty ink, sintering the drops (3) of pasty ink by laser so as to produce electrical connections (31) between the overlaid metallized vias (1).

公开(公告)号：EP2054929A2

公开(公告)日：2009-05-06

申请号：EP07788221.5

申请日：2007-08-03

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L21/98 ,  H01L25/065

CPC classification number: H01L22/32 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2221/68386 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/1461 ,  Y10T29/49004 ,  H01L2924/00

Abstract: The invention relates to the collective manufacturing of n 3D modules. It comprises a manufacturing stage of a batch of n wafers i on the same plate, of the same thickness, and comprised of silicon, covered on one test point side face (20) then an insulating layer (4) of e thickness, forming the insulating substrate and equipped with at least one electronic component (11 ) connected to the test points (20) by means of the said insulating layer, with the components being separated from each other by primary grooves (30) with a width L1, and with the connecting points of the components (2) being connected to the tracks (3) that are flush with the level of the grooves (30), (B1) a stage depositing an adhesive support (40) on the component-side face, C1 ) a stage withdrawing the silicon plate (10) so as to show the test points (20), D1 ) a stage testing the electronic components of the plate by means of the test points (20), and marking of the valid components (11 '), E1 ), a stage for reporting on an adhesive film (41), the wafers (50) each comprising a valid component (11 '), with the wafers being separated by the secondary grooves (31) at the level at which the conductive tracks (3) of the valid components (11 ') appear. This stage, repeated K times, is followed by a stage of stacking the K plates, by making metalized holes in the thickness of the stack which are intended for connecting the wafers between the K plates, then cutting the stack to obtain the n 3D modules.

公开(公告)号：EP1966825A1

公开(公告)日：2008-09-10

申请号：EP06841479.6

申请日：2006-12-19

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L23/48 ,  H01L21/98 ,  H01L25/065

CPC classification number: H01L23/3107 ,  H01L25/105 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49146 ,  Y10T29/49165 ,  Y10T29/49169 ,  H01L2924/00

Abstract: The invention relates to the collective fabrication of n 3D modules. It comprises a step of fabricating a batch of n wafers i on one and the same plate, this step being repeated K times, then a step of stacking the K plates, a step of forming plated-through holes in the thickness of the stack, these holes being intended for connecting the slices together, and then a step of cutting the stack in order to obtain the n 3D modules. The plate 10, which comprises silicon, is covered on one face 11 with an electrically insulating layer forming the insulating substrate. This face has grooves 20 that define n geometrical features, which are provided with an electronic component 1 connected to electrical connection pads 2' placed on said face. After the stacking operation, holes are drilled perpendicular to the faces of the plates vertically in line with the grooves. The size of the holes is smaller than that of the grooves so that the silicon of each wafer 10 is isolated from the wall of the hole by resin.

公开(公告)号：EP1864326A1

公开(公告)日：2007-12-12

申请号：EP06725523.2

申请日：2006-04-03

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L23/498 ,  H05K3/34 ,  H01L25/16

CPC classification number: H01L23/4985 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5387 ,  H01L25/105 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/19041 ,  H05K1/116 ,  H05K1/189 ,  H05K3/3436 ,  H05K2201/09572 ,  H05K2201/09663 ,  H05K2203/041 ,  H05K2203/0455 ,  Y02P70/613 ,  H01L2924/00

Abstract: The invention relates to an electronic module (100) comprising a pile of n packages (10, 10a, 10b) which have a predetermined thickness E and provided on the lower surface thereof with connection balls (12) having a predetermined thickness eb and connected to a printed circuit board (20, 20a, 20b) of the package interconnection. Said printed circuit board is mounted on the lower surface of the package at the ball level, comprises metallised holes (23) in which the balls (12) are arranged and to which they are connected and has a thickness eci which is less than eb, thereby making it possible to obtain a module whose thickness is equal to or less than n (E+ 10 % eb).