公开(公告)号：US20240429128A1

公开(公告)日：2024-12-26

申请号：US18340220

申请日：2023-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Satyasuresh VVss Choppalli ,  Rui Tze Toh

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H01L29/78

Abstract: Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions; a body region on a channel region between the source and drain regions; and a gate structure adjacent to and between the channel region and the dielectric material layers. Alternatively, the transistor includes: a source region between drain regions; a body region on a channel region between the source region and each drain region; and gate structures adjacent to and between the channel regions and the dielectric material layers. The first chip also includes an insulator layer on the transistor opposite the dielectric material layers, a trench in the insulator layer extending to the source and body regions, and a local interconnect at the bottom of the trench.

公开(公告)号：US20240429127A1

公开(公告)日：2024-12-26

申请号：US18340174

申请日：2023-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dewei Xu ,  Ravi Prakash Srivastava ,  Zhuojie Wu

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532

Abstract: A structure includes a through semiconductor via (TSV) in a semiconductor substrate. The structure also includes a cavity including a first cavity portion in the semiconductor substrate and surrounding a middle section of the TSV and in direct contact with the TSV. The cavity also includes a plurality of second cavity portions in the semiconductor substrate and surrounding an upper section of the TSV. The semiconductor substrate is between adjacent second cavity portions, creating a bridge portion that provides structural support. The cavity reduces parasitic capacitance.

公开(公告)号：US20240427177A1

公开(公告)日：2024-12-26

申请号：US18212437

申请日：2023-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02F1/015 ,  G02F1/025 ,  G02F1/035

Abstract: Plasmonic photonic structures that include a layer that exhibits an electric-field-induced Pockels effect and methods of forming such structures. The structure comprises a waveguide core on a substrate, a first layer that has an overlapping relationship with the first waveguide core, and a second layer that has an overlapping relationship with the first waveguide core and the first layer. The first layer comprises a metal, and the second layer comprising a material that exhibits an electric-field-induced Pockels effect.

公开(公告)号：US20240427095A1

公开(公告)日：2024-12-26

申请号：US18338712

申请日：2023-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ravi Prakash Srivastava ,  Yusheng Bian ,  Vibhor Jain

IPC: G02B6/42

Abstract: Embodiments of the disclosure provide a multi-substrate coupling for photonic integrated circuits (PICs). Structures of the disclosure may include a first substrate having a first surface. The first surface includes a groove therein. A second substrate has a second surface coupled to the first surface. The second substrate includes a cavity substantially aligned with the groove of the first surface, and a photonic integrated circuit (PIC) structure horizontally distal to the cavity.

公开(公告)号：US20240427094A1

公开(公告)日：2024-12-26

申请号：US18212754

申请日：2023-06-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Keith Donegan ,  Takako Hirokawa ,  Yusheng Bian ,  Thomas Houghton ,  Kevin Dezfulian ,  Carrie Yurkon

IPC: G02B6/42 ,  G06T7/00

Abstract: Structures including a calibration marker adjacent to a photonic structure and methods of forming such structures. The structure comprises a semiconductor substrate, a photonic structure, and a back-end-of-line stack over the semiconductor substrate. The back-end-of-line stack includes a plurality of fill features, an exclusion area surrounded by the plurality of fill features, and a calibration marker in the exclusion area. The calibration marker is disposed adjacent to the photonic structure, and the calibration marker includes a feature having a predetermined dimension.

公开(公告)号：US12176351B2

公开(公告)日：2024-12-24

申请号：US17973618

申请日：2022-10-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ryan Sporer ,  George R. Mulfinger ,  Yusheng Bian

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L27/146 ,  H01L29/06

Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

公开(公告)号：US20240419023A1

公开(公告)日：2024-12-19

申请号：US18209680

申请日：2023-06-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02F1/035

Abstract: Photonics chip structures including an edge coupler and a layer that exhibits an electric-field-induced Pockels effect and methods of forming such structures. The structure comprises a substrate, an edge coupler on the substrate, and a layer including a portion that has an overlapping relationship with the edge coupler. The layer comprises a material that exhibits an electric-field-induced Pockels effect.

公开(公告)号：US20240402421A1

公开(公告)日：2024-12-05

申请号：US18802210

申请日：2024-08-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Thomas Houghton ,  Yusheng Bian

IPC: G02B6/12 ,  G02B6/30 ,  G02B6/42 ,  G02B6/43

Abstract: A photonic integrated circuit (PIC) die are provided. The PIC die includes a set of optical connect grooves including a first groove aligning a core of a first optical fiber positioned with a first optical component in a first layer at a first vertical depth in a plurality of layers of a body of the die, and a second groove aligning a core of a second optical fiber positioned therein with a second optical component in a second, different layer at a second different vertical depth in the plurality of layers. The grooves may also have end faces at different lateral depths from an edge of the body of the PIC die. Any number of the first and second grooves can be used to communicate an optical signal to any number of layers at different vertical and/or lateral depths within the body of the PIC die.

公开(公告)号：US12158442B2

公开(公告)日：2024-12-03

申请号：US17929404

申请日：2022-09-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhuojie Wu

IPC: G01N27/22

Abstract: An integrated circuit (IC) structure includes a moisture barrier about active circuitry. A capacitor is entirely inside the moisture barrier. The capacitor has a breakdown voltage. A moisture detector is configured to apply an increasing voltage ramp to the capacitor up to a maximum voltage less than the breakdown voltage of the capacitor. In response to determining that a current hump exists in a test current-voltage response curve of the capacitor to the increasing voltage ramp, the detector transmits a signal to the active circuitry to indicate a presence of moisture in the IC structure. The moisture detector is accurate and sensitive to moisture ingress, which provides more time for remedial action. The detector is non-destructive and can be used in a final IC product.

公开(公告)号：US20240395932A1

公开(公告)日：2024-11-28

申请号：US18322212

申请日：2023-05-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： John L. LEMON ,  Hong YU ,  Haiting WANG ,  Hui ZHAN

IPC: H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wraparound gate structure and methods of manufacture. The structure includes: a channel region comprising semiconductor material; an isolation structure surrounding the channel region; a divot within the isolation structure; and a gate structure comprising gate material within the divot and surrounding the channel region.