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公开(公告)号：AU2003244421A8
公开(公告)日：2003-09-02
申请号：AU2003244421
申请日：2003-01-30
Applicant: PHILIPS INTELLECTUAL PROPERTY
Inventor： JANSSEN MARC , HAACKE MICHAEL
IPC: H01J61/16 , F21S8/10 , H01J1/62 , H01J61/00 , H01J61/20 , H01J61/24 , H01J61/34 , H01J61/35 , H01J61/40 , H01J61/52 , H01J61/82 , H01J61/84 , H01J63/04
Abstract: A mercury-free high-pressure gas discharge lamp (HID [high intensity discharge] lamp) is described which is provided for use in automotive technology. To achieve improved lamp characteristics, in particular a substantially equal luminous efficacy in comparison with lamps of the same power and a mercury-free gas filling, as well as a highest possible burning voltage, the discharge vessel (1) is provided in its wall regions (10) which are lowermost in the operational position with a coating (15) which reflects at least a portion of the infrared radiation generated during operation, such that the temperature of the coldest spots, and in particular of the light-generating substances collected there, is raised, with the result that the light-generating substances can enter the gas phase in sufficient quantities also without mercury, and in particular with the use of a metal halide as a voltage-gradient generator.
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公开(公告)号：AU2003205960A1
公开(公告)日：2003-09-02
申请号：AU2003205960
申请日：2003-02-03
Applicant: PHILIPS INTELLECTUAL PROPERTY
Inventor： KUHN HANS-JURGEN , ZUPKE MANFRED
IPC: H04N5/53
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公开(公告)号：DE10206875A1
公开(公告)日：2003-08-28
申请号：DE10206875
申请日：2002-02-18
Applicant: PHILIPS INTELLECTUAL PROPERTY
Inventor： ZINKE MANFRED , HEUTS PATRICK , FUHRMANN PETER
Abstract: The invention describes a method for the monitoring and management of data traffic in a communication system with several communication nodes which communicate via interfaces monitored by a bus monitor, comprising the following steps: a) provision of a predefined communication time schedule for all communication nodes, b) initialization of the bus monitor, c) synchronization of the communication time schedule of the bus monitor with the predefined communication time schedule executed by the communication nodes in a distributed arrangement, the synchronization taking place on the basis of activities observed at the interfaces, d) monitoring of the activities of the communication nodes by the bus monitor, e) comparison of the activities with the predefined communication time schedule, and f) deactivation of the interface for any communication node for which an activity not compatible with the predefined communication time schedule has been detected. A circuit arrangement and its use are also described.
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公开(公告)号：DE59710434D1
公开(公告)日：2003-08-21
申请号：DE59710434
申请日：1997-07-21
Applicant: PHILIPS INTELLECTUAL PROPERTY
Inventor： WILLE DR , MALZAHN RALF , QUISQATER PROF , FERREIRA RONALD
Abstract: The computer unit (3) is coupled to the microprocessor (2) via a number of registers (201,202,...), of which the first register serves to control the data transfer and the second register transfers instructions. At least two sets of first and second registers are provided. The registers of the different sets are selectively written to by the microprocessor. A third register which can be selectively written to bit-wise by the microprocessor contains information enabling selection of a set of first and second registers for controlling data and instruction transfers.
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公开(公告)号：DE10204924A1
公开(公告)日：2003-08-21
申请号：DE10204924
申请日：2002-02-07
Applicant: PHILIPS INTELLECTUAL PROPERTY
Inventor： THELEN ERIC , KLAKOW DIETRICH , SCHOLL HOLGER , WAIBEL ULI , REISINGER JOSEF
Abstract: The invention relates to a method and a device for the transcription of spoken and written utterances. To this end, the utterances undergo speech or text recognition, and the recognition result (ME) is combined with a manually created transcription (MT) of the utterances in order to obtain the transcription. The additional information rendered usable by the combination as a result of the recognition result (ME) enables the transcriber to work relatively roughly and therefore quickly on the manual transcription. When using a keyboard ( 25 ), he can, for example, restrict himself to hitting the keys of only one row and/or can omit some keystrokes completely. In addition, the manual transcribing can also be accelerated by the suggestion of continuations ( 31 ) to the text input so far ( 30 ), which continuations are anticipated by virtue of the recognition result (ME).
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Patent Agency Ranking
公开(公告)号：DE20307698U1
公开(公告)日：2003-08-14
申请号：DE20307698
申请日：2003-05-16
Applicant: PHILIPS INTELLECTUAL PROPERTY
Abstract: A belt pulley (1) comprises two parallel metal disks (2, 3) with central openings (6), a metal transmission element (7) passing without contact through these openings, and an injection molded plastics element (8) joining the two parallel disks and, at the same time, electrically insulating them from one another with a specified resistance.
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公开(公告)号：DE10204294A1
公开(公告)日：2003-08-14
申请号：DE10204294
申请日：2002-02-02
Applicant: PHILIPS INTELLECTUAL PROPERTY
Inventor： BEIER RALF
IPC: H03K3/0231 , H03K4/06 , H03K3/53
Abstract: The invention relates to a circuit arrangement for pulse generation, having a capacitor, to which a charging current and a discharging current may be supplied in succession. To generate the charging current and the discharging current, there are provided a current source, a first current mirror circuit and a second current mirror circuit complementary to the first current mirror circuit. The current mirror circuits each comprise a plurality of output transistors, which each constitute an output stage for the charging and discharging current, which is connected to a regulator, and for a circuit for controlling the tail current of a differential amplifier forming the regulator. A current output of the differential amplifier is connected to the output of the second current mirror circuit.
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公开(公告)号：AU2003201066A1
公开(公告)日：2003-07-30
申请号：AU2003201066
申请日：2003-01-14
Applicant: PHILIPS INTELLECTUAL PROPERTY
Inventor： HAPKE FRIEDRICH
IPC: G01R31/28 , G01R31/3181 , G01R31/3183 , G01R31/3185 , G01R31/3187
Abstract: An integrated circuit ( 14 ) with an application circuit ( 1 ) to be tested and a self-testing circuit ( 5 - 13 ), which is provided for testing the application circuit ( 1 ) and generates pseudorandom test patterns, which can be transformed, by means of first logic gates ( 6, 7, 8 ) and signals externally fed to said gates, into deterministic test vectors, which are fed to the application circuit ( 1 ) for testing purposes, wherein the output signals occurring through the application circuit ( 1 ) as a function of the test patterns are evaluated by means of a signature register ( 13 ), wherein, by means of second logic gates ( 10, 11, 12 ) and signals fed to said gates, those bits of the output signals of the application circuit ( 1 ) which, due to the circuit structure of application circuit ( 1 ), have undefined states, are blocked during testing.
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公开(公告)号：AU2002353401A1
公开(公告)日：2003-07-30
申请号：AU2002353401
申请日：2002-12-23
Applicant: PHILIPS INTELLECTUAL PROPERTY
Inventor： NOWOTTNICK JURGEN
IPC: G07C9/00
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公开(公告)号：DE10202336A1
公开(公告)日：2003-07-24
申请号：DE10202336
申请日：2002-01-23
Applicant: PHILIPS INTELLECTUAL PROPERTY
Inventor： ELEND BERND
Abstract: Opposite and equal currents are forced on first (7) and second (8) bus lines. A first source (5) of voltage supplies voltage. A second source (6) of voltage/current controls the opposite and equal currents and generates data bits on the bus lines. Negative-positive-negative transistors (3,4) link to a minus pole on the emitter side. Triggered by the second source of voltage/current, positive-negative-positive transistors (1,2) generate two equal collector currents, one (I1) for the first bus line and a second (IT1) for an input for a current mirror circuit.
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