公开(公告)号：US20040228167A1

公开(公告)日：2004-11-18

申请号：US10836324

申请日：2004-05-03

Applicant: Renesas Technology Corp.

Inventor： Ken Saito ,  Yoshio Inoue ,  Koji Hirakimoto

IPC: G11C011/00

CPC classification number: G06F17/5072 ,  H01L27/0203

Abstract: An automatic floor-planning method includes extracting a register and a logic operation cell in a semiconductor integrated-circuit unit, extracting a first register set and a second register set that are assumed to input and receive a signal to and from the logic operation cell directly or via other logic operation cell, respectively, creating a set of the logic operation cells as a cluster cell, determining a layout of the cluster cell and the register, selecting a logic level block for which a floor plan is performed, and determining an arrangement and wiring area such that the arrangement and wiring area of the logic level block includes as many cells as possible that belong to the logic level block.

Abstract translation: 自动楼层规划方法包括提取半导体集成电路单元中的寄存器和逻辑运算单元，提取假设为直接从逻辑运算单元输入和接收信号的第一寄存器组和第二寄存器组 或经由其他逻辑运算单元，创建一组逻辑运算单元作为集群单元，确定集群单元和寄存器的布局，选择执行平面图的逻辑电平块，以及确定布置 和布线区域，使得逻辑电平块的布置和布线区域包括属于逻辑电平块的尽可能多的单元。

公开(公告)号：US20040223506A1

公开(公告)日：2004-11-11

申请号：US10431460

申请日：2003-05-08

Applicant: Renesas Technology Corp.

Inventor： Go Sato

IPC: H04L012/54

CPC classification number: H04L47/34 ,  H04L1/1809 ,  H04L47/10 ,  H04L47/193 ,  H04L47/323 ,  H04L69/16 ,  H04L69/163

Abstract: A switching function determines whether to use delayed acknowledgment in following processing on the basis of whether received data is a nullsuccessivenull or nullnon-successivenull type of data. That is, when the type of the received data is nullsuccessive,null delayed acknowledgment is basically used in the processing. On the other hand, when the type of the received data is nullnon-successive,null delayed acknowledgment is basically not used. When the received data is nullnon-successive,null a normal receiving processing is performed according to TCP.

Abstract translation: 切换功能基于接收数据是否是“连续”或“非连续”类型的数据来确定在后续处理中是否使用延迟确认。 也就是说，当接收到的数据的类型是“连续的”时，在处理中基本上使用延迟确认。 另一方面，当接收到的数据的类型是“不连续”时，基本上不使用延迟确认。 当接收到的数据是“不连续的”时，根据TCP执行正常的接收处理。

公开(公告)号：US20040223366A1

公开(公告)日：2004-11-11

申请号：US10861452

申请日：2004-06-07

Applicant: Renesas Technology Corp.

Inventor： Seiji Miura ,  Kazushige Ayukawa

IPC: G11C011/00

CPC classification number: G06F12/0246 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/005 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40607 ,  G11C11/412 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C29/70

Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

公开(公告)号：US20040217802A1

公开(公告)日：2004-11-04

申请号：US10851156

申请日：2004-05-24

Applicant: Renesas Technology Corp.

Inventor： Kiyoo Itoh ,  Hiroyuki Mizuno

IPC: H03K003/01

CPC classification number: G11C5/146 ,  G05F3/205 ,  G11C5/147 ,  H01L27/092 ,  H02M3/073 ,  H03K19/0013 ,  H03K19/0016 ,  H03K19/00315

Abstract: The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.

Abstract translation: 当电源接通时，在正常操作期间以及当电源电压被切断时，控制具有低阈值电压MOSFET的CMOS电路的阱电压。 因此，CMOS电路可以以更低的功耗稳定地运行，因为当将电源电压施加到CMOS电路时或者当电源电压被切断时，锁存减小，并且在正常操作期间亚阈值电流减小。

公开(公告)号：US20040217411A1

公开(公告)日：2004-11-04

申请号：US10859122

申请日：2004-06-03

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Jun Ohtani ,  Tsukasa Ooishi

IPC: H01L029/76

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

Abstract: A non-volatile semiconductor memory device of the present invention is provided with a semiconductor substrate having a main surface, an ONO film (a laminated film of an oxide film, a nitride film and an oxide film) formed on the main surface and having a charge storage part, a pair of buried diffusion bit lines formed in the semiconductor substrate located on both sides of the ONO film, oxide films deposited on the main surface so as to cover the buried diffusion bit lines, and a transfer gate electrode formed on the ONO film.

Abstract translation: 本发明的非挥发性半导体存储器件具有主表面，形成在主表面上的ONO膜（氧化膜层叠膜，氮化膜和氧化膜）的半导体基板，具有 电荷存储部分，形成在位于ONO膜两侧的半导体衬底中的一对掩埋扩散位线，沉积在主表面上以覆盖掩埋扩散位线的氧化膜，以及形成在 ONO电影。

公开(公告)号：US20040215909A1

公开(公告)日：2004-10-28

申请号：US10825674

申请日：2004-04-16

Applicant: Renesas Technology Corp.

Inventor： Tsutomu Imai ,  Akira Kanehira ,  Kunihiro Katayama

IPC: G06F012/14

CPC classification number: G06F21/10 ,  G06F12/1416 ,  G06F21/725 ,  G06F2221/2137 ,  G06F2221/2153

Abstract: The disclosed invention effectively prevents fraudulent access to data whose usage is restricted to a time limit, such access attempted by manipulating the clock internal to a playback device and a terminal device. A nonvolatile memory device of the invention comprises a control circuit and a nonvolatile memory circuit which includes a storage region for restriction information to restrict access to contents information provided by web-based rental service. The restriction information includes access time limit information and access time stamp information. The control circuit performs an access decision action which comprises deciding whether access to the contents information is enabled or disabled, based on real time information which is supplied externally and the restriction information, and updating the access time stamp information to the real time information. The control circuit decides that access is disabled if the real time information is later than the access time limit given by the access time limit information or if the real time information is earlier than the access time stamp given by the access time stamp information; otherwise, the control circuit decides that the access is enabled. The control circuit performs the access decision action, at least, at the start of access to said contents information and at the end of the access.

Abstract translation: 所公开的发明有效地防止对使用限制在时间限制的数据的欺骗性访问，这种访问通过操纵播放设备和终端设备内部的时钟而尝试。 本发明的非易失性存储装置包括控制电路和非易失性存储器电路，其包括用于限制对由基于web的租赁服务提供的内容信息的访问的限制信息的存储区域。 限制信息包括访问时间限制信息和访问时间戳信息。 控制电路执行接入决策动作，其包括基于外部提供的实时信息和限制信息来决定对内容信息的访问是否被启用或禁用，以及将访问时间戳信息更新为实时信息。 如果实时信息晚于由访问时间限制信息给出的访问时间限制或者实时信息早于由访问时间戳信息给出的访问时间戳，则控制电路决定访问被禁用; 否则，控制电路确定访问被启用。 至少在开始访问所述内容信息和访问结束时，控制电路执行访问决策动作。

公开(公告)号：US20040214095A1

公开(公告)日：2004-10-28

申请号：US10847294

申请日：2004-05-18

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Shuji Nakao

IPC: G03B027/68 ,  G03F009/00 ,  G03B027/54

CPC classification number: G03F7/706 ,  G03F1/44 ,  G03F1/50

Abstract: A photomask for aberration measurement of the present invention comprises a substrate that allows exposure light to pass through, a plurality of aperture patterns for measurement that are formed on the top surface of substrate in a plurality of measurement pattern formation regions, a light blocking film that is formed in the measurement pattern formation regions on the rear surface of substrate and that has a rear surface aperture pattern for substantially differentiating the respective incident angles of the exposure light to plurality of aperture patterns for measurement and a plurality of reference patterns that is formed in a single, or in a plurality, of reference pattern formation region(s) on the top surface of substrate, wherein the rear surface of substrate in the reference pattern formation region(s) is formed so that the respective incident angles of the exposure light to plurality of reference patterns becomes the substantially the same.

Abstract translation: 本发明的像差测量用光掩模包括允许曝光光通过的基板，在多个测量图案形成区域中形成在基板的顶表面上的多个用于测量的孔径图案，遮光膜， 形成在基板后表面上的测量图案形成区域中，并且具有用于将曝光光的各个入射角度与多个测量用孔径图案基本上微分的后表面孔径图案，以及多个基准图案形成在 基板顶表面上的单个或多个参考图案形成区域，其中基准图形形成区域中的基板的后表面被形成为使得曝光光的各个入射角 到多个参考图案变得基本相同。

公开(公告)号：US20040213064A1

公开(公告)日：2004-10-28

申请号：US10671795

申请日：2003-09-29

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Takayuki Gyohten ,  Masaru Haraguchi ,  Fukashi Morishita

IPC: G11C007/00

CPC classification number: G11C11/4096 ,  G11C7/06 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2207/065

Abstract: A connection gate circuit includes first and second N channel MOS transistors connected in series between a first bit line of a pair of bit lines and a first global IO line of a pair of IO lines, and third and fourth N channel MOS transistors connected in series between a second bit line of the pair of bit lines and a second global IO line of the pair of IO lines. The first and second N channel MOS transistors have their gates receiving a sense amplifier activation signal activating a sense amplifier. The third and fourth N channel MOS transistors have their gates receiving a column selection signal.

Abstract translation: 连接门电路包括串联连接在一对位线的第一位线和一对IO线的第一全局IO线之间的第一和第二N沟道MOS晶体管，以及串联连接的第三和第四N沟道MOS晶体管 在所述一对位线的第二位线与所述一对IO线的第二全局IO线之间。 第一和第二N沟道MOS晶体管的栅极接收激活读出放大器的读出放大器激活信号。 第三和第四N沟道MOS晶体管的栅极接收列选择信号。

公开(公告)号：US20040212436A1

公开(公告)日：2004-10-28

申请号：US10849852

申请日：2004-05-21

Applicant: Renesas Technology Corp. ,  Hitachi Communications Systems, Inc.

Inventor： Yoshikuni Matsunaga ,  Toshihiko Shimizu ,  Tomio Furuya ,  Nobuhiro Matsudaira ,  Koichi Matsushita

IPC: H03G003/10

CPC classification number: H03F1/0261 ,  H03F2200/465 ,  H03G1/0017 ,  H03G3/3042 ,  H03G3/3047

Abstract: A multistage high frequency power amplifier-circuit device has a plurality of semiconductor amplification elements connected in a cascade. The circuit device is provided with a bias control circuit used to control the bias voltage or bias current of the output semiconductor amplification element in each stage so as to reduce the variation of the output power with respect to the power control signal voltage in an area around the threshold voltage of the semiconductor amplification elements. This realizes a high frequency power amplifier circuit device provided with excellent controllability of the output power and high efficiency at the time of low power output realized with use of such a control voltage as a power control signal.

Abstract translation: 多级高频功率放大器电路装置具有串联连接的多个半导体放大元件。 电路装置设置有偏置控制电路，用于控制各级输出半导体放大元件的偏置电压或偏置电流，以便减少相对于周围区域内的功率控制信号电压的输出功率的变化 半导体放大元件的阈值电压。 这实现了在使用诸如功率控制信号的这种控制电压实现的低功率输出时，输出功率具有优异的可控制性和高效率的高频功率放大器电路器件。

公开(公告)号：US20040212434A1

公开(公告)日：2004-10-28

申请号：US10820026

申请日：2004-04-08

Applicant: Renesas Technology Corp.

Inventor： Hiroyuki Nagamori ,  Yasuhiro Nunogawa ,  Takayuki Tsutsui

IPC: H03G003/10

CPC classification number: H03F3/195 ,  H03F1/301 ,  H03F3/193 ,  H03F3/602 ,  H03G3/3042

Abstract: There are provided an electronic component for high frequency power amplification provided with a high-sensitivity output power detection circuit which is immune to the influence of changes in the use environment thereof, free of an output mismatch, small in size, and low in insertion loss and a wireless communication system using the electronic component. There are provided an output detection transistor which receives, at a control terminal, a voltage extracted from the intermediate node of an impedance matching circuit provided between the final-stage power amplification transistor of a high-frequency power amplification circuit and an output terminal thereof via a capacitor element and allows a current proportional to an output power to flow, a bias generation circuit for giving an operating point to the control terminal of the transistor, a current mirror circuit for transferring the current flowing in the output detection transistor, and a current-to-voltage conversion transistor for converting the transferred current to a voltage.

Abstract translation: 提供了一种高频功率放大的电子元件，其具有高灵敏度的输出功率检测电路，其免受其使用环境变化的影响，没有输出失配，尺寸小，插入损耗低 以及使用该电子部件的无线通信系统。 提供了一种输出检测晶体管，其在控制端子处接收从设置在高频功率放大电路的最后级功率放大晶体管和其输出端之间的阻抗匹配电路的中间节点提取的电压 电容器元件并且允许与输出功率成比例的电流流动;用于给晶体管的控制端施加工作点的偏置产生电路，用于传送在输出检测晶体管中流动的电流的电流镜电路，以及电流 电压转换晶体管，用于将传输的电流转换成电压。