公开(公告)号：WO2015171362A1

公开(公告)日：2015-11-12

申请号：PCT/US2015/027974

申请日：2015-04-28

Applicant: SOITEC ,  STMICROELECTRONICS, INC.

Inventor： ALLIBERT, Frederic ,  MORIN, Pierre

IPC: H01L21/84

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02614 ,  H01L21/02694 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/205

Abstract: Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.

Abstract translation: 制造半导体结构的方法包括形成具有不同应力/应变状态的finFET晶体管的翅片。 可以使用一个应力/应变状态的芯来形成n型finFET，而可以采用另一个应力/应变状态的翅片来形成p型finFET。 具有不同应力/应变状态的翅片可以由公共半导体材料层制造。 使用这种方法制造半导体结构和器件。

公开(公告)号：WO2014172132A1

公开(公告)日：2014-10-23

申请号：PCT/US2014/033181

申请日：2014-04-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES, INC.

Inventor： CHENG, Kangguo ,  DORIS, Bruce, B. ,  KHAKIFIROOZ, Ali ,  LIU, Qing ,  LOUBET, Nicolas ,  LUNING, Scott

IPC: H01L21/76 ,  H01L21/8232 ,  H01L21/8238

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: A method for semiconductor fabrication includes providing (404) channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed (406) for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

Abstract translation: 一种用于半导体制造的方法包括在包括至少一个硅锗（SiGe）沟道区的衬底上提供（404）沟道区，所述衬底包括包括第一区和第二区的多个区域。 在第一区域中形成用于第一n型场效应晶体管（NFET）和第一p型场效应晶体管（PFET）的栅极结构（406），在第二区域中形成第二NFET和第二PFET，栅极 用于在SiGe沟道区上形成第一PFET的结构。 用于第一NFET的栅极结构包括具有第一功函数的栅极材料，并且用于第一PFET，第二NFET和第二PFET的栅极结构包括具有第二功函数的栅极材料，使得提供多阈值电压器件。

公开(公告)号：WO2014039033A1

公开(公告)日：2014-03-13

申请号：PCT/US2012/053767

申请日：2012-09-05

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS, INC. ,  VINET, Maud ,  LOUBET, Nicolas ,  WACQUEZ, Romain

Inventor： VINET, Maud ,  LOUBET, Nicolas ,  WACQUEZ, Romain

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/823481 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/66772

Abstract: A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second monocrystalline semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer and the dielectric layer, and such that the trench delimits one active region of the microelectronic device, chemical vapor etching of the second semiconductor layer, at the level of the bottom wall of the trench, according to at least two crystalline planes of the second semiconductor layer such that an etched part of the second semiconductor layer extends under a part of the active region, filling of the trench and of said etched part of the second semiconductor layer with a dielectric material.

Abstract translation: 一种在包括第一半导体层，电介质层和第二单晶半导体层的衬底中制造微电子器件的方法，包括以下步骤：通过第一半导体层和电介质层蚀刻沟槽，并且使得沟槽限定 根据所述第二半导体层的至少两个晶面，所述微电子器件的一个有源区域，所述第二半导体层的所述第二半导体层的所述第二半导体层的蚀刻部分在所述沟槽的底壁的水平面上进行化学气相蚀刻， 在有源区域的一部分下延伸，用介电材料填充沟槽和第二半导体层的所述蚀刻部分。

公开(公告)号：WO2012067625A1

公开(公告)日：2012-05-24

申请号：PCT/US2010/057441

申请日：2010-11-19

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS, INC. ,  DESTEFANIS, Vincent ,  LOUBET, Nicolas

Inventor： DESTEFANIS, Vincent ,  LOUBET, Nicolas

IPC: H01L21/00

CPC classification number: H01L21/0226 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02642

Abstract: The deposition method comprises providing a substrate with a first mono-crystalline zone made of a semiconductor material and a second zone made of an insulating material. During a passivation step, a passivation atmosphere is applied on the substrate so as to cover the first zone with doping impurities. During a deposition step, gaseous silicon and/or germanium precursors are introduced and a doped semiconductor film is formed. The semiconductor film is mono-crystalline over the first zone and has a different texture over the second zone. During an etching step, a chloride gaseous precursor is applied on the substrate so as to remove the semiconductor layer over the second zone.

Abstract translation: 沉积方法包括提供具有由半导体材料制成的第一单晶区和由绝缘材料制成的第二区的衬底。 在钝化步骤期间，钝化气氛被施加在衬底上，以便用掺杂杂质覆盖第一区域。 在沉积步骤期间，引入气态硅和/或锗前体并形成掺杂半导体膜。 半导体膜在第一区域上是单晶的，并且在第二区域上具有不同的纹理。 在蚀刻步骤期间，将氯化物气体前体施加在衬底上，以便在第二区域上移除半导体层。

公开(公告)号：WO2014131461A1

公开(公告)日：2014-09-04

申请号：PCT/EP2013/054113

申请日：2013-02-28

Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： VINET, Maud ,  CHENG, Kangguo ,  DORIS, Bruce ,  GRENOUILLET, Laurent ,  KHAKIFIROOZ, Ali ,  LE TIEC, Yannick ,  LIU, Qing

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/8238

CPC classification number: H01L27/12 ,  H01L21/762 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0653

Abstract: The invention relates to an integrated circuit (9), including: - a first cell, comprising: - FDSOI transistors (1c, 1d); - a UTBOX layer (4) lying beneath said transistors; - a first well (94) lying beneath the insulator layer (4) and beneath said transistors, said first well having a first type of doping; - a first ground plane (32) having a second type of doping, located beneath one of said transistors and between the insulator layer (4) and the first well (94); - a first STI (25) separating said transistors and crossing said insulator layer; - a first conductive element (33) forming an electrical connection between the first well (94) and the first ground plane (32), located under said first STI (25); - a second cell including a second well (93); - a second STI (24) separating said cells, crossing said insulator layer (4) and reaching the bottom of said first and second wells.

Abstract translation: 本发明涉及一种集成电路（9），包括： - 第一单元，包括： - FDSOI晶体管（1c，1d）; - 位于所述晶体管下方的UTBOX层（4） - 位于绝缘体层（4）下方并位于所述晶体管下方的第一阱（94），所述第一阱具有第一类型的掺杂; - 具有第二类型掺杂的第一接地平面（32），位于所述晶体管中的一个之下，以及绝缘体层（4）和第一阱（94）之间; - 分离所述晶体管并与所述绝缘体层交叉的第一STI（25） - 形成位于所述第一STI（25）下方的第一阱（94）和第一接地平面（32）之间的电连接的第一导电元件（33）。 - 包括第二井（93）的第二池; - 隔离所述电池的第二STI（24），穿过所述绝缘体层（4）并到达所述第一和第二阱的底部。

公开(公告)号：WO2014074096A1

公开(公告)日：2014-05-15

申请号：PCT/US2012/064110

申请日：2012-11-08

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS, INC.

Inventor： VINET, Maud ,  MIGNOT, Sylvie ,  WACQUEZ, Romain

IPC: H01L21/336

CPC classification number: H01L21/76283 ,  H01L21/311 ,  H01L21/76232 ,  H01L21/84 ,  H01L29/0649

Abstract: Method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a first dielectric layer and a second semiconductor layer, comprising the following steps: etching of a trench through the first semiconductor layer, the first dielectric layer and a part of the second semiconductor layer, defining one active region, and such that, at the level of the second semiconductor layer, a part of the trench extends under a part of the active region, etching of the second dielectric layer such that remaining portions of the second dielectric layer forms portions of dielectric material extending under a part of the active region, deposition of a third dielectric layer in the trench such that the trench is filled with the dielectric materials of the second and third dielectric layers and forms an isolation trench.

Abstract translation: 在包括第一半导体层，第一介电层和第二半导体层的衬底中制造微电子器件的方法，包括以下步骤：通过第一半导体层，第一电介质层和第二电介质层的一部分蚀刻沟槽 半导体层，限定一个有源区，并且使得在第二半导体层的一级，沟槽的一部分在有源区的一部分之下延伸，蚀刻第二介电层，使得第二介电层的剩余部分 形成在有源区的一部分下方延伸的电介质材料的部分，在沟槽中沉积第三电介质层，使得沟槽被第二和第三电介质层的电介质材料填充并形成隔离沟槽。

公开(公告)号：WO2006031329A2

公开(公告)日：2006-03-23

申请号：PCT/US2005/028368

申请日：2005-08-10

Applicant: STMICROELECTRONICS, INC. ,  AXALTO ,  FRUHAUF, Serge ,  LEYDIER, Robert, A.

Inventor： FRUHAUF, Serge ,  LEYDIER, Robert, A.

IPC: G06F13/40 ,  G06F13/38 ,  G06K19/07

CPC classification number: G06F13/4068

Abstract: A USB device, integrated circuit, smart card and method are disclosed. A USB transceiver is connected to a data interface and operable at a respective low speed and full speed configuration. A processor as a USB device controller is operatively connected to the low speed USB transceiver and full speed USB transceiver and operable for transmitting a different device descriptor to a USB host for performing an enumeration depending on whether a low speed or high speed operation is chosen.

Abstract translation: 公开了一种USB设备，集成电路，智能卡和方法。 USB收发器连接到数据接口并可在相应的低速和全速配置下操作。 作为USB设备控制器的处理器可操作地连接到低速USB收发器和全速USB收发器，并且可操作用于根据是否选择低速或高速操作来向USB主机发送不同的设备描述符以执行枚举。

公开(公告)号：WO2014162164A1

公开(公告)日：2014-10-09

申请号：PCT/IB2013/001017

申请日：2013-04-03

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERIGES ALTERNATIVES ,  STMICROELECTRONICS INC

Inventor： VINET, Maud ,  GRENOUILLET, Laurent ,  LIU, Qing

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/8238

CPC classification number: H01L29/41783 ,  H01L21/31133 ,  H01L21/32 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/6656

Abstract: A method for manufacturing a microelectronic device with transistors of different types having raised source and drain regions and different overlap regions.

Abstract translation: 一种用于制造具有不同类型的具有升高的源极和漏极区域以及不同重叠区域的晶体管的微电子器件的方法。

公开(公告)号：WO2014131459A1

公开(公告)日：2014-09-04

申请号：PCT/EP2013/054081

申请日：2013-02-28

Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： VINET, Maud ,  CHENG, Kangguo ,  DORIS, Bruce ,  GRENOUILLET, Laurent ,  KHAKIFIROOZ, Ali ,  LE TIEC, Yannick ,  LIU, Qing

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/8238

CPC classification number: H01L27/1203 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0928 ,  H01L29/0649

Abstract: The invention relates to an integrated circuit (9), including: -a UTBOX layer (4); -a first cell, comprising: -FDSOI transistors (1a, 1b); -a first STI (23) separating said transistors; -a first ground plane (31) located beneath one of said transistors and beneath said UTBOX layer (4); -a first well (93); -a second cell, comprising : -FDSOI transistors (1c, 1d); -a second STI (25) separating said transistors; -a second ground plane (32) located beneath one of said transistors and beneath said UTBOX layer (4); -a second well (94); -a third STI (24) separating said cells, reaching the bottom of said first and second wells (93, 94); -a deep well (92) extending continuously beneath said first and second wells, having a portion (33) beneath said third STI (24) whose doping density is at least 50% higher than the doping density of the deep well beneath said first and second STIs.

Abstract translation: 本发明涉及一种集成电路（9），包括： - 一个UTBOX层（4）; - 第一电池，包括：-FDSOI晶体管（1a，1b）; - 分离所述晶体管的第一STI（23） - 位于所述晶体管中的一个之下并位于所述UTBOX层（4）下方的第一接地平面（31）。 - 第一口井（93）; - 第二电池，包括：-FDSOI晶体管（1c，1d）; - 分离所述晶体管的第二STI（25） - 位于所述晶体管中的一个之下并位于所述UTBOX层（4）下方的第二接地平面（32）; 第二口（94）; - 分离所述细胞的第三STI（24），到达所述第一和第二孔（93,94）的底部; - 深井（92），其在所述第一和第二井下方连续延伸，具有在所述第三STI（24）下方的部分（33），所述第三STI（24）的掺杂密度比所述第一和第二阱下面的深井的掺杂密度高至少50％ 第二STIs。

公开(公告)号：WO2014039034A1

公开(公告)日：2014-03-13

申请号：PCT/US2012/053768

申请日：2012-09-05

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS, INC. ,  GRENOUILLET, Laurent ,  LE TIEC, Yannick ,  LOUBET, Nicolas ,  VINET, Maud ,  WACQUEZ, Romain

Inventor： GRENOUILLET, Laurent ,  LE TIEC, Yannick ,  LOUBET, Nicolas ,  VINET, Maud ,  WACQUEZ, Romain

IPC: H01L31/0376

CPC classification number: H01L21/76283 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/84

Abstract: A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps : etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, - filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.

Abstract translation: 一种在包括第一半导体层，电介质层和第二半导体层的衬底中制造微电子器件的方法，包括以下步骤：通过所述第一半导体层，所述电介质层和所述第一半导体层的厚度的一部分蚀刻沟槽 从而在所述第一半导体层中限定所述微电子器件的一个有源区域，在所述沟槽的一个或多个侧壁中的离子注入，在所述第二半导体层的水平处，修改所述晶体学性质和/或所述第二半导体层， 注入半导体的化学性质，蚀刻注入的半导体，使得沟槽的至少一部分在有源区的一部分下延伸; - 用介电材料填充沟槽，形成围绕有源区的隔离沟槽，并且包括 在有源区域的一部分下延伸的部分。