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    DATA PROCESSING SYSTEMS
    225.
    发明专利
    DATA PROCESSING SYSTEMS 未知

    公开(公告)号：GB1498116A

    公开(公告)日：1978-01-18

    申请号：GB1420175

    申请日：1975-04-07

    Applicant: HONEYWELL INF SYSTEMS

    IPC: G06F9/46 ,  G06F12/10 ,  G06F12/1036 ,  G06F12/14 ,  G06F9/18 ,  G06F13/00

    Abstract: 1498116 Memory arrangement HONEYWELL INFORMATION SYSTEMS Inc 7 April 1975 [18 April 1974] 14201/75 Heading G4A Program segments are stored in virtual memory partitions, each program segment being defined by a descriptor which specifies a partition register which holds the identity of the partition containing the relevant segment, identifies the appropriate storage location by its base address within the partition and its size, and specifies access rights in reading, writing, altering and executing of the program segment; each user is assigned access to a limited number of memory partitions whose identities are held in respective partition registers. The output of the specified partition register is an address in a partition page table (Fig. 9, not shown) which which provides the real memory address of a page reference table for that partition which cross-references virtual page addresses to real memory addresses. Certain of the memory partitions may be shared by all users, others being exclusively assigned to users. A procedure in execution may transfer access to certain program segments to a called procedure by transferring the descriptors defining the segments to the called procedure. Access to a segment by a called procedure may be restricted to part of the segment by altering the descriptor to increase the base address or reduce the indicated size. The descriptors are stored in three segments 70, 72, 74 each associated with a register 71, 73, 75. In routine execution descriptors from segments 70, 72, 74 are loaded in registers 78 and reference program segments in virtual space 80, the real memory addresses of which are derived using the page reference tables 82. Descriptors to be passed to a called procedure are passed, either intact or altered to restrict access to part of the segment, to segment 74. Upon execution of a call instruction the current procedure is interrupted, the contents of registers 71, 73, 75 are stored at 86 for subsequent return, and the descriptors to be passed are transferred from segment 74 to segment 72, register 71 being loaded with the appropriate descriptor from segment 70 or 72 to identify the new segment 70.

    226.
    发明专利
    未知

    公开(公告)号：DE1774212B2

    公开(公告)日：1973-01-25

    申请号：DE1774212

    申请日：1968-05-03

    IPC: G06F12/10 ,  G06F12/1036 ,  G06F9/00

    Two-stage address translation
    229.
    发明专利
    Two-stage address translation 未知

    公开(公告)号：IL312735A

    公开(公告)日：2024-07-01

    申请号：IL31273524

    申请日：2024-05-09

    Applicant: ADVANCED RISC MACH LTD ,  GRISENTHWAITE RICHARD ROY

    Inventor： GRISENTHWAITE RICHARD ROY

    IPC: G06F12/1036 ,  G06F12/109 ,  G06F12/14 ,  G06F21/53 ,  G06F21/74

    Abstract: Memory management circuitry supports two-stage address translation based on a stage-1 and stage-2 translation table structures. Stage-2 access permission information specified by a stage-2 translation table entry has an encoding specifying whether a corresponding memory region has a partially-read-only permission indicating that write requests to the memory region corresponding to the target intermediate address, issued when processing circuitry is in a predetermined execution state, are permitted for a restricted subset of write request types (including metadata-updating write requests for updating access tracking metadata in translation table entries) but prohibited for other write request types. The memory management circuitry rejects a memory access request when the stage-2 access permission information of a corresponding stage-2 translation table entry specifies the partially-read-only permission and the memory access request is a write request, other than the restricted subset of write request types, issued in the predetermined execution state.

    Apparatus and method
    230.
    发明专利
    Apparatus and method 未知

    公开(公告)号：IL296346A

    公开(公告)日：2022-11-01

    申请号：IL29634622

    申请日：2022-09-08

    Applicant: ADVANCED RISC MACH LTD ,  ELAD YUVAL ,  PARKER JASON ,  GRISENTHWAITE RICHARD ROY ,  CRASKE SIMON JOHN ,  CHADWICK ALEXANDER DONALD CHARLES

    Inventor： ELAD YUVAL ,  PARKER JASON ,  GRISENTHWAITE RICHARD ROY ,  CRASKE SIMON JOHN ,  CHADWICK ALEXANDER DONALD CHARLES

    IPC: G06F12/1009 ,  G06F12/1036 ,  G06F12/14

    Abstract: An apparatus comprises translation circuitry to perform a translation operation to generate a translated second (e.g. physical or intermediate) memory address within a second memory address space as a translation of a first memory address (e.g. intermediate or virtual) within a first memory address space, in which the translation circuitry is configured to generate the translated second memory address in dependence upon translation information stored at one or more translation information addresses. Permission circuitry performs an operation to detect permission information to indicate, for a given second memory address, whether memory access is permitted to the given second memory address. Access circuitry allows access to data stored at the given second memory address when the permission information indicates that memory access is permitted to the given second memory address, and is configured to selectively allow access by the translation circuitry to a translation information address without the permission circuitry having completed the operation to detect permission information to indicate whether memory access is permitted to that translation information address, which may be a read or a write address.

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