公开(公告)号：CA1092719A

公开(公告)日：1980-12-30

申请号：CA292248

申请日：1977-12-02

Applicant: IBM

Inventor： GANNON PATRICK M ,  HELLER ANDREW R ,  SMITH RONALD M

IPC: G06F12/10 ,  G06F13/00

Abstract: SYNONYM CONTROL MEANS FOR MULTIPLE VIRTUAL STORAGE SYSTEMS The embodiments relate to special controls in a processor which eliminate synonym entries in a translation lookaside buffer (DLAT) and their corresponding page duplication in main storage for a system which has DLAT entries that can concurrently translate virtual addresses in multiple address spaces into real main storage addresses. The controls provide a common space bit in any segment table entry (STE) or alternatively in any page table entry (PTE) in any private address space to indicate whether the segment or page, respectively, contains programs and data private to the address space or shared by all address spaces. Each DLAT entry contains a common/private storage indicator which is set to the state of the common space bit in the STE or PTE used in an address translation loaded into the DLAT entry. When the entry is read, the private/common storage indicator controls whether the DLAT can only be used by the address space identified in the DLAT, or by all address spaces.

公开(公告)号：FR2394128A1

公开(公告)日：1979-01-05

申请号：FR7813287

申请日：1978-04-27

Applicant: IBM

Inventor： GANNON PATRICK M ,  SY KIAN-BON K

IPC: G06F12/08 ,  G06F9/34 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06F9/06

公开(公告)号：DE3584657D1

公开(公告)日：1991-12-19

申请号：DE3584657

申请日：1985-07-23

Applicant: IBM

Inventor： BRANDT HENRY R ,  GANNON PATRICK M ,  LEUNG WAN L ,  MARCHINI TIMOTHY R

IPC: G06F12/10 ,  G06F12/14

Abstract: The disclosure provides a unique high-speed hardware dynamic address translation mechanism (DATM) arrangement for generating double-level address translations (i.e. guest virtual/guest absolute = host virtual/host absolute address translations) in combination with a translation look- aside buffer (TLB) structure that can store and lookup intermediate translations during a double-level translation. The hardware proceeds to the completion of a double-level translation without having to backup its operation, although an intermediate TLB miss is encountered, and without danger of CPU deadlock occurring. The hardware arrangement (DATM) also performs all single-level address translations required by the system.

公开(公告)号：CA1229424A

公开(公告)日：1987-11-17

申请号：CA482002

申请日：1985-05-21

Applicant: IBM

Inventor： BRANDT HENRY R ,  GANNON PATRICK M ,  LEUNG WAN L ,  MARCHINI TIMOTHY R

IPC: G06F12/10 ,  G06F12/14

Abstract: The disclosure provides a unique high-speed hardware arrangement for generating double-level address translations in combination with a translation look-aside buffer (TLB) structure that can store and lookup intermediate translations during a double-level translation. The hardware proceeds to the completion of a double-level translation without having to backup its operation, although an intermediate TLB miss is encountered, without danger of CPU deadlock occurring. The hardware arrangement also performs all single-level address translations required by the system.

公开(公告)号：FR2423822A1

公开(公告)日：1979-11-16

申请号：FR7905120

申请日：1979-02-22

Applicant: IBM

Inventor： GANNON PATRICK M ,  LIPTAY JOHN S ,  RYMARCZYK JAMES W

IPC: C08F4/46 ,  G06F9/308 ,  G06F9/312 ,  G06F9/345 ,  G06F9/38 ,  G06F12/04 ,  G06F12/08 ,  G06F12/0855 ,  G06F12/0886 ,  G06F9/06 ,  G11C9/06

公开(公告)号：FR2385147A1

公开(公告)日：1978-10-20

申请号：FR7804190

申请日：1978-02-08

Applicant: IBM

Inventor： GANNON PATRICK M ,  HELLER ANDREW R ,  SMITH RONALD M ,  SITE RICHARD L

IPC: G06F12/10 ,  G06F12/1036 ,  G06F9/20

Abstract: Special controls in a processor prevent synonym entries in a translation look aside buffer (DLAT) for a system which has DLAT entries that can concurrently translate virtual page addresses in multiple address spaces into real main storage page frame addresses. The controls use a synonym resolution register (SRR) which divides each address space in the system into common and private portions. Fields in the SRR indicate which portions are to be common to all address spaces, and which portions are private in each address space. A SRR control circuit selects a particular status field under control of a virtual address requesting main storage access.

公开(公告)号：CA986230A

公开(公告)日：1976-03-23

申请号：CA180753

申请日：1973-09-11

Applicant: IBM

Inventor： AHEARN THOMAS P ,  CHRISTENSEN NEAL T ,  GANNON PATRICK M ,  LEE ARLIN E ,  LIPTAY JOHN S ,  CAPOWSKI ROBERT S

IPC: G06F12/10

Abstract: This specification describes a virtual memory system in which a set of conversion tables is used to translate an arbitrarily assigned programming designation called a virtual address into an actual main memory location called a real address. To avoid the necessity of translating the same addresses over and over again, a table called the Directory Look Aside Table (DLAT) retains current virtual to real address translations for use where particular virtual addresses are requested more than once. Each translation retained by the DLAT is identified by an identifier (ID) that signifies the set of tables used in that translation. This identifier is compared with an identifier generated for the currently requested virtual address. If these identifiers match and the virtual address retained in the DLAT matches the currently requested virtual address, the translation stored in the DLAT may be used. If the identifiers or virtual address don't match, a new translation must be performed using the set of conversion tables associated with the currently requested address.