公开(公告)号：US11610564B2

公开(公告)日：2023-03-21

申请号：US17383806

申请日：2021-07-23

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Altug Koker ,  Kiran C. Veernapu ,  Erik G. Liskay

IPC: G09G5/39 ,  G06F3/14 ,  G06T1/20 ,  G09G5/393

Abstract: A mechanism is described for facilitating consolidated compression/de-compression of graphics data streams of varying types at computing devices. A method of embodiments, as described herein, includes generating a common sector cache relating to a graphics processor. The method may further include performing a consolidated compression of multiple types of graphics data streams associated with the graphics processor using the common sector cache.

公开(公告)号：US11609856B2

公开(公告)日：2023-03-21

申请号：US17206514

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Prasoonkumar Surti ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Abhishek R. Appu ,  Nicolas C. Galoppo Von Borries ,  Joydeep Ray ,  Narayan Srinivasa ,  Feng Chen ,  Ben J. Ashbaugh ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Altug Koker

IPC: G06F12/08 ,  G06F12/0837 ,  G06N3/08 ,  G06N20/00 ,  G06T1/20 ,  G06F12/0815 ,  G06N3/063 ,  G06N3/04 ,  G06N3/084 ,  G06N3/088

Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.

公开(公告)号：US11605197B2

公开(公告)日：2023-03-14

申请号：US17180188

申请日：2021-02-19

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Joydeep Ray ,  John H. Feit ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  Philip R. Laws

IPC: G06T15/00 ,  H04N13/398 ,  H04N13/344

Abstract: An embodiment of a parallel processor apparatus may include a sample pattern selector to select a sample pattern for a pixel, and a sample pattern subset selector communicatively coupled to the sample pattern selector to select a first subset of the sample pattern for the pixel corresponding to a left eye display frame and to select a second subset of the sample pattern for the pixel corresponding to a right eye display frame, wherein the second subset is different from the first subset. Other embodiments are disclosed and claimed.

公开(公告)号：US11593269B2

公开(公告)日：2023-02-28

申请号：US17400415

申请日：2021-08-12

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06F12/0802 ,  G06F12/0855 ,  G06F12/0806 ,  G06F12/0846 ,  G06F12/0868 ,  G06T1/60 ,  G06F12/126 ,  G06F12/0893

Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

公开(公告)号：US11592817B2

公开(公告)日：2023-02-28

申请号：US15581124

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Altug Koker ,  Farshad Akhbari ,  Feng Chen ,  Dukhwan Kim ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Mike B. Macpherson ,  Linda L. Hurd ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G05D1/00 ,  G06F9/50 ,  G06N3/084

Abstract: A mechanism is described for facilitating storage management for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting one or more components associated with machine learning, where the one or more components include memory and a processor coupled to the memory, and where the processor includes a graphics processor. The method may further include allocating a storage portion of the memory and a hardware portion of the processor to a machine learning training set, where the storage and hardware portions are precise for implementation and processing of the training set.

公开(公告)号：US20230039853A1

公开(公告)日：2023-02-09

申请号：US17968469

申请日：2022-10-18

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Brandon Fliflet ,  James Valerio ,  Michael Apodaca ,  Ben Ashbaugh ,  Hema Nalluri ,  Ankur Shah ,  Murali Ramadoss ,  David Puffer ,  Altug Koker ,  Aditya Navale ,  Abhishek R. Appu ,  Joydeep Ray ,  Travis Schluessler

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06F9/52 ,  G06T1/60

Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.

公开(公告)号：US11574386B2

公开(公告)日：2023-02-07

申请号：US17239800

申请日：2021-04-26

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Balaji Vembu ,  Prasoonkumar Surti

IPC: G06T15/00 ,  G06T3/40 ,  G06F3/01 ,  G06T15/50

Abstract: Systems, apparatuses and methods may provide away to blend two or more of the scene surfaces based on the focus area and an offload threshold. More particularly, systems, apparatuses and methods may provide a way to blend, by a display engine, two or more of the focus area scene surfaces and blended non-focus area scene surfaces. The systems, apparatuses and methods may include a graphics engine to render the focus area surfaces at a higher sample rate than the non-focus area scene surfaces.

公开(公告)号：US20230027960A1

公开(公告)日：2023-01-26

申请号：US17816960

申请日：2022-08-02

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Travis T. Schluessler ,  Prasoonkumar Surti ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  James M. Holland ,  Jeffery S. Boles ,  Jonathan Kennedy ,  Louis Feng ,  Atsuo Kuwahara ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Gokcen Cilingir ,  Nilesh V. Shah ,  Archie Sharma ,  Mayuresh M. Varerkar

IPC: H04S7/00 ,  G06T1/20 ,  G06T15/06 ,  G06F3/01 ,  H04R1/40 ,  H04R3/00 ,  G09B21/00

Abstract: Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

公开(公告)号：US11561828B2

公开(公告)日：2023-01-24

申请号：US17317387

申请日：2021-05-11

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Varghese George ,  Altug Koker ,  Aravindh Anantaraman ,  SungYe Kim ,  Valentin Andrei ,  Joydeep Ray

IPC: G06F9/48 ,  G06F9/38 ,  G06F12/0837 ,  G06F9/30 ,  G06F9/50

Abstract: Accelerated synchronization operations using fine grain dependency check are disclosed. A graphics multiprocessor includes a plurality of execution units and synchronization circuitry that is configured to determine availability of at least one execution unit. The synchronization circuitry to perform a fine grain dependency check of availability of dependent data or operands in shared local memory or cache when at least one execution unit is available.

公开(公告)号：US20220413994A1

公开(公告)日：2022-12-29

申请号：US17358845

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： John Wiegert ,  Joydeep Ray ,  Fabian Schnell ,  Kelvin Thomas Gardiner

IPC: G06F11/36 ,  G06F9/30

Abstract: An apparatus to facilitate watchpoints for debugging in a graphics environment is disclosed. The apparatus includes processing resources to perform graphics operations using a plurality of threads; and load store pipeline hardware circuitry coupled to the processing resources to: configure a watchpoint register with a value of a watchpoint address, the watchpoint address comprising an address of a memory location in the processor; receive a memory access request from a thread of the plurality of threads; determine, using the watchpoint register, whether the memory access request is requesting access to the watchpoint address; and responsive to the memory access request requesting access to the watchpoint address, return an exception payload to the thread, the exception payload comprising watchpoint details corresponding to the watchpoint address and a scoreboard identifier (SBID) associated with the memory access request.