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    MERGING ATOMICS TO THE SAME CACHE LINE
    2.
    发明公开
    MERGING ATOMICS TO THE SAME CACHE LINE 审中-公开

    公开(公告)号：US20240087077A1

    公开(公告)日：2024-03-14

    申请号：US17944542

    申请日：2022-09-14

    Applicant: Intel Corporation

    Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Prathamesh Raghunath Shinde ,  John Wiegert

    IPC: G06T1/60 ,  G06T1/20

    CPC classification number: G06T1/60 ,  G06T1/20

    Abstract: Embodiments described herein provide a technique to merge partial cache line writes to a cache memory. One embodiment provides a graphics processor comprising a graphics core, a cache coupled with the graphics core, and memory access circuitry to process memory access messages received from the graphics core. The memory access circuitry includes partial cache line write merge circuitry configured to merge a first partial write to a cache line of the cache with a second partial write to the cache line of the cache.

    WATCHPOINTS FOR DEBUGGING IN A GRAPHICS ENVIRONMENT
    4.
    发明申请
    WATCHPOINTS FOR DEBUGGING IN A GRAPHICS ENVIRONMENT 有权

    公开(公告)号：US20220413994A1

    公开(公告)日：2022-12-29

    申请号：US17358845

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： John Wiegert ,  Joydeep Ray ,  Fabian Schnell ,  Kelvin Thomas Gardiner

    IPC: G06F11/36 ,  G06F9/30

    Abstract: An apparatus to facilitate watchpoints for debugging in a graphics environment is disclosed. The apparatus includes processing resources to perform graphics operations using a plurality of threads; and load store pipeline hardware circuitry coupled to the processing resources to: configure a watchpoint register with a value of a watchpoint address, the watchpoint address comprising an address of a memory location in the processor; receive a memory access request from a thread of the plurality of threads; determine, using the watchpoint register, whether the memory access request is requesting access to the watchpoint address; and responsive to the memory access request requesting access to the watchpoint address, return an exception payload to the thread, the exception payload comprising watchpoint details corresponding to the watchpoint address and a scoreboard identifier (SBID) associated with the memory access request.

    BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES
    5.
    发明公开
    BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES 审中-公开

    公开(公告)号：US20240095038A1

    公开(公告)日：2024-03-21

    申请号：US17949904

    申请日：2022-09-21

    Applicant: Intel Corporation

    Inventor： John Wiegert ,  Joydeep Ray ,  Timothy Bauer ,  James Valerio

    IPC: G06F15/78 ,  G06F9/30

    CPC classification number: G06F15/7839 ,  G06F9/30043

    Abstract: Embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. The 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. The memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.

    EXCEPTION HANDLING FOR DEBUGGING IN A GRAPHICS ENVIRONMENT
    8.
    发明申请
    EXCEPTION HANDLING FOR DEBUGGING IN A GRAPHICS ENVIRONMENT 有权

    公开(公告)号：US20250118003A1

    公开(公告)日：2025-04-10

    申请号：US18919846

    申请日：2024-10-18

    Applicant: Intel Corporation

    Inventor： John Wiegert ,  Joydeep Ray ,  Fabian Schnell ,  Kelvin Thomas Gardiner

    IPC: G06T1/20 ,  G06F9/30 ,  G06F11/34 ,  G06T1/60

    Abstract: An apparatus to facilitate exception handling for debugging in a graphics environment is disclosed. The apparatus includes load store pipeline hardware circuitry to: in response to a page fault exception being enabled for a memory access request received from a thread of the plurality of threads, allocate a memory dependency token correlated to a scoreboard identifier (SBID) that is included with the memory access request; send, to memory fabric of the graphics processor, the memory access request comprising the memory dependency token; receive, from the memory fabric in response to the memory access request, a memory access response comprising the memory dependency token and indicating occurrence of a page fault error condition and fault details associated with the page fault error condition; and return the SBID associated with the memory access response and fault details of the page fault error condition to a debug register of the thread.

    Exception handling for debugging in a graphics environment
    10.
    发明授权
    Exception handling for debugging in a graphics environment 有权

    公开(公告)号：US12154207B2

    公开(公告)日：2024-11-26

    申请号：US17358811

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： John Wiegert ,  Joydeep Ray ,  Fabian Schnell ,  Kelvin Thomas Gardiner

    IPC: G06T15/00 ,  G06F9/30 ,  G06F9/38 ,  G06T1/60

    Abstract: An apparatus to facilitate exception handling for debugging in a graphics environment is disclosed. The apparatus includes load store pipeline hardware circuitry to: in response to a page fault exception being enabled for a memory access request received from a thread of the plurality of threads, allocate a memory dependency token correlated to a scoreboard identifier (SBID) that is included with the memory access request; send, to memory fabric of the graphics processor, the memory access request comprising the memory dependency token; receive, from the memory fabric in response to the memory access request, a memory access response comprising the memory dependency token and indicating occurrence of a page fault error condition and fault details associated with the page fault error condition; and return the SBID associated with the memory access response and fault details of the page fault error condition to a debug register of the thread.

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