公开(公告)号：DE60012084D1

公开(公告)日：2004-08-19

申请号：DE60012084

申请日：2000-05-11

Applicant: ST MICROELECTRONICS INC

Inventor： WENZEL EDWARD P

IPC: H02M3/28 ,  H02M1/10 ,  H02M3/335 ,  H02M7/00

Abstract: A power supply includes an AC supply circuit and an AC input having a rectifier. An isolation output transformer has first and second primary winding terminals and a low voltage winding section for connecting to a DC voltage input that is lower than the range of the DC voltage from the rectifier. The rectifier is connected to the first primary winding of the transformer. A transistor is connected to the second primary winding of the transformer. The DC supply circuit includes a DC input selectably connectable between the first primary winding when the input to the DC input is a nominal DC voltage within the range of the DC bulk voltage and the low voltage winding section when the input to the DC input is lower than the range of the DC bulk voltage.

公开(公告)号：DE69723530T2

公开(公告)日：2004-06-09

申请号：DE69723530

申请日：1997-10-30

Applicant: ST MICROELECTRONICS INC

Inventor： CEDAR YORAM ,  ZIKLIK ARYE

IPC: G06F13/38 ,  G06F15/78 ,  H03K19/173 ,  H03K19/177

Abstract: A circuit connectable to a microcontroller having an address bus, a data bus, a read line and a write line including a programmable logic device (PLD) array, at least one input pin and at least one databus macrocell. The input pin is connected to the PLD array and is connectable to the address bus. The databus macrocell is connected to the PLD array and to an external unit and is also connectable to the data bus, the read line and the write line. The data bus directly accesses the databus macrocell.

公开(公告)号：DE69724318T2

公开(公告)日：2004-05-27

申请号：DE69724318

申请日：1997-03-26

Applicant: ST MICROELECTRONICS INC

Inventor： CHAN TSIU CHIU ,  ENG LAWRENCE P

IPC: G06F12/16 ,  G06F11/22 ,  G06F11/273 ,  G06F15/78 ,  G11C29/02 ,  G11C29/44 ,  G11C29/48 ,  G11C29/00 ,  G06F11/267

公开(公告)号：DE69531282T2

公开(公告)日：2004-05-27

申请号：DE69531282

申请日：1995-11-28

Applicant: ST MICROELECTRONICS INC

Inventor： CHAN TSIU CHIU

IPC: H01L21/76 ,  H01L21/336 ,  H01L21/761 ,  H01L21/765 ,  H01L27/08 ,  H01L27/118 ,  H01L29/78

Abstract: An isolation gate structure is formed between active areas on a P-type semiconductor substrate. The isolation structure includes a thick gate oxide layer over which is formed a P-doped polycrystalline silicon layer. The polycrystalline silicon layer is electrically connected to the substrate, by buried contact if desired, and can further be electrically connected to a source region formed within the active area. The polycrystalline silicon layer and substrate are connected to ground potential, thus preventing current flow between active areas.

公开(公告)号：DE69728117D1

公开(公告)日：2004-04-22

申请号：DE69728117

申请日：1997-11-27

Applicant: ST MICROELECTRONICS INC

Inventor： SUICHEONG SO JASON ,  CHAN TSIU CHIU

IPC: H01L21/8234 ,  G05F3/20 ,  G05F3/24 ,  G11C5/14 ,  H01L27/088 ,  H03K17/30

Abstract: An integrated circuit includes a plurality of MOSFETs on a substrate. A plurality of sensing MOSFETs are used to generate a plurality of comparison signals based upon comparing signals related to the sensed initial threshold voltages to respective reference voltages from a spread of high to low reference voltage values. The MOSFETs are biased to have a desired effective threshold voltage based upon the plurality of comparison signals. Logic decoding circuits accept the plurality of comparison signals and generate at least one bias control signal. Bias circuits are responsive to the at least one bias control signal for generating a desired bias voltage from among a plurality of bias voltages having a spread of high to low bias voltage values to thereby bias the plurality of MOSFETs to the desired effective threshold voltage. Method aspects of the invention are also disclosed.

公开(公告)号：DE69914425D1

公开(公告)日：2004-03-04

申请号：DE69914425

申请日：1999-08-24

Applicant: ST MICROELECTRONICS INC

Inventor： HUI DANNY K ,  HVOSTOV HARRY S ,  FUNG ANTHONY ,  GROZ PETER ,  HSU JIM C

IPC: H04L29/10 ,  G06F13/38 ,  H04L12/40 ,  H04L12/64

Abstract: A system architecture for a high speed serial bus compatible with the 1394 standard is disclosed. A transaction interface coordinates data packets received from or sent to a 1394 bus. A kernel/scheduler/dispatcher is used to allocate memory resources, and start a variety of tasks and services. The tasks and services vary depending on protocols used in a transport layer and application layer used in conjunction with the 1394 layers. The transaction interface uses information derived from the data packets received to form message control blocks, particular for each individual task, and places the control blocks into the proper task queue. The transaction interface forms a dispatcher message control block and places it into the scheduler/dispatcher queue to initiate the task. If there are no other message control blocks in the queue particular for the called task, the called task is immediately started. Otherwise, the message control block waits in the queue to eventually be operated on.

公开(公告)号：DE69726774D1

公开(公告)日：2004-01-29

申请号：DE69726774

申请日：1997-02-27

Applicant: ST MICROELECTRONICS INC

Inventor： BLANCHARD RICHARD A

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L29/866

公开(公告)号：BR0114811A

公开(公告)日：2003-12-09

申请号：BR0114811

申请日：2001-08-30

Applicant: ST MICROELECTRONICS INC ,  SCHLUMBERGER SYSTEMES S A ,  SCHLUMBERGER TECHNOLOGIES OPERATING LTD

Inventor： FRUHAUF SERGE F ,  POMET ALAIN CHRISTOPHE ,  LEYDIER ROBERT ANTONIE

IPC: G06F13/10 ,  G06K17/00 ,  G06K19/07

Abstract: A multi-mode IC is provided for operating in a first mode such as an ISO mode in accordance with International Standards Organization 7816 (ISO 7816) protocol, and a second, non-ISO mode, such as a USB mode in accordance with Universal Serial Bus (USB) protocol. The multi-mode IC is preferably in a smart card and includes a microprocessor and an external interface. The external interface comprises a voltage supply pad, a ground pad, a first set of pads for the first mode, and 2 second set of pads for the second mode. The first set of pads preferably include a reset pad, a clock pad and an input/output pad in accordance with the ISO 7816 protocol, and may also include a variable supply voltage pad in accordance with the ISO 7816 protocol. The IC further includes a mode configuration circuit for detecting a mode condition on one pad of the first set of pads, and configuring the IC in the ISO mode or the non-ISO mode depending on the result. Once the IC is configured in a particular mode, it will operate in only that mode until the next power-on reset sequence.

公开(公告)号：DE69905833T2

公开(公告)日：2003-12-04

申请号：DE69905833

申请日：1999-09-28

Applicant: ST MICROELECTRONICS INC

Inventor： NGUYEN THI N

IPC: G06F7/52 ,  G06F7/523 ,  G06F7/544

公开(公告)号：DE69719116T2

公开(公告)日：2003-11-13

申请号：DE69719116

申请日：1997-06-03

Applicant: ST MICROELECTRONICS INC ,  AMERICAN MICRO SYST

Inventor： EITAN BOAZ ,  PETERSEN LARRY WILLIS ,  SLEZAK YARON

IPC: G11C11/41 ,  G11C7/06 ,  G11C8/18 ,  G11C16/06 ,  G11C8/00

Abstract: A clock delay circuit for generating a delay for a sense amplifier release signal in an integrated circuit semiconductor memory device is disclosed. Rather than utilize traditional programmable capacitors that must be trimmed on a die by die basis, the novel clock delay circuit disclosed utilizes a small ROM, EPROM, EEPROM or FLASH array coupled to a bit line emulator to provide a clock delay matched to the larger main array. The size of the small memory array is on the order of 5 to 10 bit lines by 5 to 10 word lines. One cell within the small array is fixed to be continuously selected. The selected cell is coupled to the clock delay node along with the bit line emulator. The bit line emulator models the capacitance of the actual bit line used in the main array. However, the circuit is constructed so that a much larger signal is generated by the delay circuit such that sense amplifiers detect the correct signal. The CMOS based clock delay circuit uses the emulated array to generate a delta or margin that accurately tracks the delays within the main array with variations in temperature, supply voltage and process.