公开(公告)号：US11152430B2

公开(公告)日：2021-10-19

申请号：US16375571

申请日：2019-04-04

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe Boivin ,  Jean Jacques Fagot ,  Emmanuel Petitprez ,  Emeline Souchier ,  Olivier Weber

IPC: H01L29/73 ,  H01L27/24 ,  H01L45/00

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

公开(公告)号：US11150533B2

公开(公告)日：2021-10-19

申请号：US16931090

申请日：2020-07-16

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Frédéric Boeuf ,  Cyrille Barrera

IPC: G02F1/225 ,  G02F1/025 ,  G02F1/035

Abstract: A capacitive electro-optical modulator includes a silicon layer, a germanium or silicon-germanium strip overlying the silicon layer, and a silicon strip overlying the germanium or silicon-germanium strip. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator is laterally adjacent the germanium or silicon-germanium strip and the silicon strip and has an upper surface that is flush with an upper surface of the silicon strip. An insulating layer overlies the insulator and the silicon strip. A layer of III-V material overlies the insulating layer. The layer of III-V material is formed as a third strip arranged facing the silicon strip and separated therefrom by a portion of the insulating layer.

公开(公告)号：US11150388B2

公开(公告)日：2021-10-19

申请号：US15610150

申请日：2017-05-31

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Vincent Farys ,  Alain Inard ,  Olivier Noblanc

IPC: G02B5/02 ,  C23C16/34 ,  C23C16/56 ,  C23C18/12

Abstract: Methods of manufacture of an optical diffuser. In one embodiment, an optical diffuser is formed by providing a wafer including a silicon slice of which an upper face is covered with a first layer made of a first material itself covered with a second layer made of a second selectively etchable material with respect to the first material. The method further includes forming openings in the second layer extending up to the first layer and filling the openings in the second layer with a third material. The method yet further includes bonding a glass substrate to the wafer on the side of its upper face and removing the silicon slice.

公开(公告)号：US11145780B2

公开(公告)日：2021-10-12

申请号：US16789045

申请日：2020-02-12

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L31/113 ,  H01L31/0224 ,  H01L27/146

Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.

公开(公告)号：US11145741B2

公开(公告)日：2021-10-12

申请号：US16591371

申请日：2019-10-02

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Alexis Gauthier ,  Pascal Chevalier

IPC: H01L29/66 ,  H01L21/22 ,  H01L29/06 ,  H01L29/73

Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.

公开(公告)号：US11139303B2

公开(公告)日：2021-10-05

申请号：US17026869

申请日：2020-09-21

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Arnaud Regnier ,  Stephan Niel ,  Quentin Hubert ,  Thomas Cabout

IPC: H01L27/108 ,  H01L29/66 ,  H01L49/02 ,  H01L29/94

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

公开(公告)号：US20210305311A1

公开(公告)日：2021-09-30

申请号：US17199779

申请日：2021-03-12

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois ROY

IPC: H01L27/148 ,  H04N5/372

Abstract: A charge-coupled device includes an array of insulated electrodes vertically penetrating into a semiconductor substrate. The array includes rows of alternated longitudinal and transverse electrodes. Each end of a longitudinal electrode of a row is opposite and separated from a portion of an adjacent transverse electrode of that row. Electric insulation walls extend parallel to one another and to the longitudinal electrodes. The insulation walls penetrate vertically into the substrate deeper than the longitudinal electrodes. At least two adjacent rows of electrodes are arranged between each two successive insulation walls.

公开(公告)号：US20210305309A1

公开(公告)日：2021-09-30

申请号：US17211723

申请日：2021-03-24

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Thierry BERGER ,  Damien JEANJEAN

IPC: H01L27/146

Abstract: The present disclosure relates to a method for manufacturing a pixel that includes depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; performing chemical mechanical planarization up to the insulating layer, a portion of the electrode layer left in place in the opening forming an electrode; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.

公开(公告)号：US20210296129A1

公开(公告)日：2021-09-23

申请号：US17338379

申请日：2021-06-03

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Denis Monnier ,  Olivier Gonnard

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/285

Abstract: A exemplary semiconductor device includes a first gate structure overlying a surface of the semiconductor body, the first gate structure being silicided. A second gate structure overlies the surface of the semiconductor body and not being silicided. An oxide layer overlies the second gate structure and extends toward the first gate structure. A silicon nitride region is laterally spaced from the second gate structure and overlies a portion of the oxide layer between the first gate structure and the second gate structure.

公开(公告)号：US20210280721A1

公开(公告)日：2021-09-09

申请号：US17323545

申请日：2021-05-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mickael GROS-JEAN ,  Julien FERRAND

IPC: H01L29/78 ,  H01L21/28 ,  H01L27/07 ,  H01L29/51 ,  H01L29/66

Abstract: A method for manufacturing first and second transistors on a semiconductor substrate includes: depositing an interface layer on the semiconductor substrate; depositing a gate insulator layer on the interface layer; depositing a first ferroelectric layer on the gate insulator layer over a first region for the first transistor; depositing a metal gate layer on the gate insulator layer over a second region for the second transistor and on the first ferroelectric layer over the first region for the first transistor; and patterning the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer to form a first gate stack for the first transistor which includes the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer and a second gate stack for the second transistor which includes the metal gate layer, gate insulator layer and interface layer.